Patents by Inventor Mark L. Doczy

Mark L. Doczy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Decreased Switching Current in Spin-Transfer Torque Memory
    Publication number: 20150243336
    Abstract: Switching current in Spin-Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of the cell.
    Type: Application
    Filed: June 10, 2013
    Publication date: August 27, 2015
    Inventors: Elijah V. Karpov, Brian S. Doyle, Kaan Oguz, Satyarth Suri, Robert S. Chau, Charles S. Kuo, Mark L. Doczy, David L. Kencke
  • FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION
    Publication number: 20150236100
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Application
    Filed: May 1, 2015
    Publication date: August 20, 2015
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Perpendicular spin transfer torque memory (STTM) device having offset cells and method to form same
    Patent number: 9105839
    Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: August 11, 2015
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, David L. Kencke, Charles C. Kuo, Uday Shah, Kaan Oguz, Mark L. Doczy, Satyarth Suri, Clair Webb
  • PERPENDICULAR MTJ STACKS WITH MAGNETIC ANISOTROPHY ENHANCING LAYER AND CRYSTALLIZATION BARRIER LAYER
    Publication number: 20150194596
    Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.
    Type: Application
    Filed: March 16, 2015
    Publication date: July 9, 2015
    Inventors: Kaan OGUZ, Mark L. DOCZY, Brian DOYLE, Uday SHAH, David L. KENCKE, Roksana GOLIZADEH MOJARAD, Robert S. CHAU
  • Perpendicular spin transfer torque memory (STTM) device with enhanced stability and method to form same
    Patent number: 9054302
    Abstract: Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: June 9, 2015
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Charles C. Kuo, Kaan Oguz, Uday Shah, Elijah V. Karpov, Roksana Golizadeh Mojarad, Mark L. Doczy, Robert S. Chau
  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Patent number: 9048314
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: June 2, 2015
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Perpendicular Spin Transfer Torque Memory (STTM) Device with Coupled Free Magnetic Layers
    Publication number: 20150091110
    Abstract: Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and damping are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A first free magnetic layer is disposed above the dielectric layer. A second free magnetic layer is magnetically coupled with the first free magnetic layer.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Charles C. Kuo, Kaan Oguz, Mark L. Doczy, Brian S. Doyle, Satyarth Suri, Robert S. Chau, David L. Kencke, Roksana Golizadeh Mojarad, Anurag Chaudhry
  • Perpendicular MTJ stacks with magnetic anisotropy enhancing layer and crystallization barrier layer
    Patent number: 8980650
    Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Mark L. Doczy, Brian Doyle, Uday Shah, David L. Kencke, Roksana Golizadeh Mojarad, Robert S. Chau
  • Decreased switching current in spin-transfer torque memory
    Patent number: 8913422
    Abstract: Switching current in Spin-Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of the cell.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 16, 2014
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Brian S. Doyle, Kaan Oguz, Satyarth Suri, Robert S. Chau, Charles C. Kuo, Mark L. Doczy, David L. Kencke
  • FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION
    Publication number: 20140361363
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Application
    Filed: August 21, 2014
    Publication date: December 11, 2014
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • PERPENDICULAR MTJ STACKS WITH MAGNETIC ANISOTROPY ENHANCING LAYER AND CRYSTALLIZATION BARRIER LAYER
    Publication number: 20140349415
    Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.
    Type: Application
    Filed: August 7, 2014
    Publication date: November 27, 2014
    Inventors: Kaan Oguz, Mark L. Doczy, Brian Doyle, Uday Shah, David L. Kencke, Roksana Golizadeh Mojarad, Robert S. Chau
  • PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE HAVING OFFSET CELLS AND METHOD TO FORM SAME
    Publication number: 20140329337
    Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.
    Type: Application
    Filed: July 16, 2014
    Publication date: November 6, 2014
    Inventors: Brian S. Doyle, David L. Kencke, Charles C. Kuo, Uday Shah, Kaan Oguz, Mark L. Doczy, Satyarth Suri, Clair Webb
  • PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE WITH ENHANCED STABILITY AND METHOD TO FORM SAME
    Publication number: 20140308760
    Abstract: Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.
    Type: Application
    Filed: June 24, 2014
    Publication date: October 16, 2014
    Inventors: Brian S. Doyle, Charles C. Kuo, Kaan Oguz, Uday Shah, Elijah V. Karpov, Roksana Golizadeh Mojarad, Mark L. Doczy, Robert S. Chau
  • EXTREME HIGH MOBILITY CMOS LOGIC
    Publication number: 20140291615
    Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
    Type: Application
    Filed: June 11, 2014
    Publication date: October 2, 2014
    Inventors: Suman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Majumdar Amian, Justin K. Brask, Been-Yih Jin, Matthew V. Metz, Robert S. Chau
  • Perpendicular MTJ stacks with magnetic anisotropy enhancing layer and crystallization barrier layer
    Patent number: 8836056
    Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: September 16, 2014
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Mark L. Doczy, Brian Doyle, Uday Shah, David L. Kencke, Roksana Golizadeh Mojarad, Robert S. Chau
  • Field effect transistor with narrow bandgap source and drain regions and method of fabrication
    Patent number: 8816394
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: August 26, 2014
    Assignee: Intel Corporation
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • Extreme high mobility CMOS logic
    Patent number: 8802517
    Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: August 12, 2014
    Assignee: Intel Corporation
    Inventors: Suman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Majumdar Amian, Justin K. Brask, Been-Yih Jin, Matthew V. Metz, Robert S. Chau
  • Gate electrode having a capping layer
    Patent number: 8803255
    Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: August 12, 2014
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
  • Perpendicular spin transfer torque memory (STTM) device with enhanced stability and method to form same
    Patent number: 8796797
    Abstract: Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 5, 2014
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Charles C. Kuo, Kaan Oguz, Uday Shah, Elijah V. Karpov, Roksana Golizadeh Mojarad, Mark L. Doczy, Robert S. Chau
  • Perpendicular spin transfer torque memory (STTM) device having offset cells and method to form same
    Patent number: 8786040
    Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 22, 2014
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, David L. Kencke, Charles C. Kuo, Uday Shah, Kaan Oguz, Mark L. Doczy, Satyarth Suri, Clair Webb