Patents by Inventor Mark L. Doczy

Mark L. Doczy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
    Patent number: 7785958
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, a trench within the first dielectric layer, and a second dielectric layer on the substrate. The second dielectric layer has a first part that is formed in the trench and a second part. After a first metal layer with a first workfunction is formed on the first and second parts of the second dielectric layer, part of the first metal layer is converted into a second metal layer with a second workfunction.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: August 31, 2010
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Justin K. Brask, Jack Kavalieros, Uday Shah, Matthew V. Metz, Suman Datta, Ramune Nagisetty, Robert S. Chau
  • Highly-selective metal etchants
    Patent number: 7741230
    Abstract: A highly selective metal wet etchant with an active ingredient comprising one or more types of molecules having two or more oxygen atoms is described. In one embodiment, the wet etchant is utilized to pattern a metal layer in a semiconductor structure. In another embodiment, a highly selective metal wet etchant with an active ingredient comprising one or more types of molecules having two or more oxygen atoms is used to pattern a metal gate electrode in a replacement gate processing scheme.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: June 22, 2010
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Jack T. Kavalieros, Mark Y. Liu, Mark L. Doczy
  • FORMING ABRUPT SOURCE DRAIN METAL GATE TRANSISTORS
    Publication number: 20100151669
    Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
    Type: Application
    Filed: February 26, 2010
    Publication date: June 17, 2010
    Inventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
  • Lateral undercut of metal gate in SOI device
    Patent number: 7736956
    Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 15, 2010
    Assignee: Intel Corporation
    Inventors: Suman Datta, Justin K. Brask, Jack Kavalieros, Brian S. Doyle, Gilbert Dewey, Mark L. Doczy, Robert S. Chau
  • Forming integrated circuits with replacement metal gate electrodes
    Patent number: 7718479
    Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Robert S. Chau
  • Method for making a semiconductor device having a high-k gate dielectric
    Patent number: 7709909
    Abstract: A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Gilbert Dewey, Suman Datta, Sangwoo Pae, Justin K. Brask, Jack Kavalieros, Matthew V. Metz, Adrian B. Sherrill, Markus Kuhn, Robert S. Chau
  • Method of forming abrupt source drain metal gate transistors
    Patent number: 7704833
    Abstract: A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventors: Nick Lindert, Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Justin K. Brask, Robert S. Chau, Mark Bohr, Anand S. Murthy
  • Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode
    Patent number: 7671471
    Abstract: A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is formed within the trench on a first part of the second dielectric layer. A second metal layer is then formed on the first metal layer and on a second part of the second dielectric layer.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: March 2, 2010
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Uday Shah, Chris E. Barns, Matthew V. Metz, Suman Datta, Annalisa Cappellani, Robert S. Chau
  • FIELD EFFECT TRANSISTOR WITH METAL SOURCE/DRAIN REGIONS
    Publication number: 20090325350
    Abstract: A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.
    Type: Application
    Filed: May 2, 2008
    Publication date: December 31, 2009
    Inventors: Marko Radosavljevic, Suman Datta, Brian S. Doyle, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Amian Majumdar, Robert S. Chau
  • CMOS DEVICE WITH METAL AND SILICIDE GATE ELECTRODES AND A METHOD FOR MAKING IT
    Publication number: 20090280608
    Abstract: A semiconductor device and a method for forming it are described. The semoiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.
    Type: Application
    Filed: November 2, 2006
    Publication date: November 12, 2009
    Inventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Matthew V. Metz, Chris E. Barns, Uday Shah, Suman Datta, Christopher D. Thomas, Robert S. Chau
  • Forming high-k dielectric layers on smooth substrates
    Patent number: 7615441
    Abstract: A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: November 10, 2009
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Gilbert Dewey, Robert S. Chau
  • Complementary Metal Oxide Semiconductor Integrated Circuit Using Raised Source Drain and Replacement Metal Gate
    Publication number: 20090261391
    Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the removal of a nitride etch stop layer.
    Type: Application
    Filed: June 29, 2009
    Publication date: October 22, 2009
    Inventors: Jack KAVALIEROS, Annalisa CAPPELLANI, Justin K. BRASK, Mark L. DOCZY, Matthew V. METZ, Suman DATTA, Chris E. BARNS, Robert S. CHAU
  • Removing a high-k gate dielectric
    Patent number: 7575991
    Abstract: A metal oxide layer on a substrate is converted at least partly to a metal layer. At least part of the metal layer is covered by an oxidation resistant cover. The covered layer and underlying metal may be removed, for example, using acid.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: August 18, 2009
    Assignee: Intel Corporation
    Inventors: Mark L. Doczy, Robert L. Norman, Justin K. Brask, Jack Kavalieros, Matthew Metz, Suman Datta, Robert S. Chau
  • Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate
    Patent number: 7569443
    Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the-removal of a nitride etch stop layer.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: August 4, 2009
    Assignee: Intel Corporation
    Inventors: Jack Kavalieros, Annalisa Cappellani, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Chris E. Barns, Robert S. Chau
  • METAL GATE DEVICE WITH REDUCED OXIDATION OF A HIGH-K GATE DIELECTRIC
    Publication number: 20090179282
    Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such as spacer formation and annealing of ion implanted regions.
    Type: Application
    Filed: January 14, 2009
    Publication date: July 16, 2009
    Inventors: Brian S. Doyle, Jack Kavalieros, Justin K. Brask, Matthew V. Mertz, Mark L. Doczy, Suman Datta, Robert S. Chau
  • METHODS FOR FABRICATING PMOS METAL GATE STRUCTURES
    Publication number: 20090166769
    Abstract: Methods of forming a microelectronic structure are described. Those methods may include forming a gate dielectric layer on a substrate, forming a metal gate layer on the gate dielectric layer, and then forming a polysilicon layer on the metal gate layer in situ, wherein the metal gate layer is not exposed to air.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Applicant: INTEL CORPORATION
    Inventors: Matthew V. Metz, Mark L. Doczy, Gilbert Dewey, Jack Kavalieros
  • Reducing Ambipolar Conduction in Carbon Nanotube Transistors
    Publication number: 20090159872
    Abstract: Ambipolar conduction can be reduced in carbon nanotube transistors by forming a gate electrode of a metal. Metal sidewall spacers having different workfunctions than the gate electrode may be formed to bracket the metal gate electrode.
    Type: Application
    Filed: January 26, 2009
    Publication date: June 25, 2009
    Inventors: Suman Datta, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Marko Radosavljevic, Amlan Majumdar, Justin K. Brask, Robert S. Chau
  • FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION
    Publication number: 20090142897
    Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 4, 2009
    Inventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
  • GATE ELECTRODE HAVING A CAPPING LAYER
    Publication number: 20090121297
    Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
    Type: Application
    Filed: January 15, 2009
    Publication date: May 14, 2009
    Inventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
  • Gate electrode having a capping layer
    Patent number: 7524727
    Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: April 28, 2009
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz