Abstract: A method including determining a test duration for testing each of a plurality of memory arrays individually coupled to a plurality of array built-in-self test (ABIST) engines, the test duration is equal to a time period required by each of the plurality of ABIST engines to test each of the plurality of memory arrays, determining a corresponding delay value for each of the plurality of ABIST engines, each of the corresponding delay values is based on the test duration for each of the plurality of memory arrays, and consecutively delaying the start of processing of each of the plurality of ABIST engines by providing each of the corresponding delay values to each of a plurality of programmable delay units individually coupled to each of the plurality of ABIST engines, the start of processing of each of the plurality of ABIST engines is delayed by a different corresponding delay value.

Abstract: A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads.

Abstract: A wafer probe alignment system and method for aligning a probe to a chip wafer for testing a chip on the wafer are provided. At least two corners of the probe are adjustable in a same direction in relation to a primary corner of the probe. The alignment approach includes providing a grid of signal pins for corresponding contact pads of the chip under test, determining for each signal pin whether an electrical contact is established to a corresponding contact pad of the chip under contact force, and adjusting a position of each of the at least two corners by a corner individual delta position value with respect to the direction depending on a result of the determining in order to establish an electrical contact between each of the pins and the corresponding contact pads of the chip under test.

Abstract: A water probe alignment system and method for aligning a probe to a chip wafer for testing a chip on the wafer are provided. At least two corners of the probe are adjustable in a same direction in relation to a primary corner of the probe. The alignment approach includes providing a grid of signal pins for corresponding contact pads of the chip under test, determining for each signal pin whether an electrical contact is established to a corresponding contact pad of the chip under contact force, and adjusting a position of each of the at least two corners by a corner individual delta position value with respect to the direction depending on a result of the determining in order to establish an electrical contact between each of the pins and the corresponding contact pads of the chip under test.

Abstract: Embodiments of the present invention provide systems and methods for a RAM at speed flexible timing and setup control. The memory module includes: a module connected to a functional logic circuitry; first timing control latches of a first scan-in chain; a timing configuration circuitry controllable by timing and control configuration signals; selection circuits connected to each output line of the first timing control latches; and an output signal of the timing configuration circuitry is connected to input lines of the selection circuits, such that two sets of control data are operatively connected to the control input lines of the memory cells under test, without a reloading of the respective timing control latches.

Abstract: Embodiments of the present invention provide systems and methods for a RAM at speed flexible timing and setup control. The memory module includes: a module connected to a functional logic circuitry; first timing control latches of a first scan-in chain; a timing configuration circuitry controllable by timing and control configuration signals; selection circuits connected to each output line of the first timing control latches; and an output signal of the timing configuration circuitry is connected to input lines of the selection circuits, such that two sets of control data are operatively connected to the control input lines of the memory cells under test, without a reloading of the respective timing control latches.

Abstract: Embodiments of the present invention provide methods, program products, and systems for testing a memory cell arrangement. Embodiments of the present invention can determine categories of memory fail conditions by checking memory cells of with a sequence of test parameter configurations for a malfunction using test parameters, storing for test parameter configurations for which a malfunction is detected, and assigning the respective test parameter configuration with a bit fail count comprising the number of malfunctioning memory cells. Embodiments of the present invention can be used to create a relational data structure representing test parameter configurations and can combine one or more test parameter configurations and can create a representation of the bit fail counts of the respective test parameter configurations.

Abstract: Embodiments of the present invention provide systems and methods for a RAM at speed flexible timing and setup control. The memory module includes: a module connected to a functional logic circuitry; first timing control latches of a first scan-in chain; a timing configuration circuitry controllable by timing and control configuration signals; selection circuits connected to each output line of the first timing control latches; and an output signal of the timing configuration circuitry is connected to input lines of the selection circuits, such that two sets of control data are operatively connected to the control input lines of the memory cells under test, without a reloading of the respective timing control latches.

Abstract: Embodiments of the present invention provide systems and methods for a RAM at speed flexible timing and setup control. The memory module includes: a module connected to a functional logic circuitry; first timing control latches of a first scan-in chain; a timing configuration circuitry controllable by timing and control configuration signals; selection circuits connected to each output line of the first timing control latches; and an output signal of the timing configuration circuitry is connected to input lines of the selection circuits, such that two sets of control data are operatively connected to the control input lines of the memory cells under test, without a reloading of the respective timing control latches.

Abstract: A module plate is provided for use with a wafer handler and testing mechanism. The module plate has a diameter equivalent to an integrated circuit wafer and a height equivalent to or less than a height of a module lid associated with each module in a plurality of modules associated with the module plate. The module plate has a plurality of cutouts in the module plate that have a width equivalent to a width of the module lid and at least a length equivalent to a length of the module lid. The height of the module plate is such that, when a test head contacts a module base of each module in a plurality of modules, the module lid contacts a chuck on which the module plate resides during testing of the module thereby providing resistance in order to accurately test the module.

Abstract: A module plate is provided for use with a wafer handler and testing mechanism. The module plate has a diameter equivalent to an integrated circuit wafer and a height equivalent to or less than a height of a module lid associated with each module in a plurality of modules associated with the module plate. The module plate has a plurality of cutouts in the module plate that have a width equivalent to a width of the module lid and at least a length equivalent to a length of the module lid. The height of the module plate is such that, when a test head contacts a module base of each module in a plurality of modules, the module lid contacts a chuck on which the module plate resides during testing of the module thereby providing resistance in order to accurately test the module.

Abstract: A method for soldering three-dimensional integrated circuits is provided. A three-dimensional integrated circuit is heated to a base temperature, wherein the base temperature is lower than the melting point of a solder, and wherein the three-dimensional integrated circuit includes a plurality of solder bumps. A first on-chip heat source reflows a first portion of the plurality of solder bumps that is within a first local-hot-zone. A second on-chip heat source reflows a second portion of the plurality of solder bumps that is within a second local-hot-zone.

Abstract: A method for soldering three-dimensional integrated circuits is provided. A three-dimensional integrated circuit is heated to a base temperature, wherein the base temperature is lower than the melting point of a solder, and wherein the three-dimensional integrated circuit includes a plurality of solder bumps. A first on-chip heat source reflows a first portion of the plurality of solder bumps that is within a first local-hot-zone. A second on-chip heat source reflows a second portion of the plurality of solder bumps that is within a second local-hot-zone.

Abstract: Embodiments of the present invention provide methods, program products, and systems for testing a memory cell arrangement. Embodiments of the present invention can determine categories of memory fail conditions by checking memory cells of with a sequence of test parameter configurations for a malfunction using test parameters, storing for test parameter configurations for which a malfunction is detected, and assigning the respective test parameter configuration with a bit fail count comprising the number of malfunctioning memory cells. Embodiments of the present invention can be used to create a relational data structure representing test parameter configurations and can combine one or more test parameter configurations and can create a representation of the bit fail counts of the respective test parameter configurations.

Abstract: A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.

Abstract: A method and system which provide a personalized indicator datum on at least one terminal when establishing a telecommunication or when setting up a call between at least two terminals. In a first database, able to be accessed by an intelligent network of the network of the first terminal, an identification datum assigned to a first terminal is assigned the identification datum of at least one second terminal. And, as a function of the assignment, at least one indicator datum is stored in the first or a further database able to be accessed by the intelligent network of the TCN of the first terminal. When a call set-up is initiated between at least two terminals, in response to the identification datum of the first terminal, the intelligent network of the TCN of the first terminal compares the identification datum of the at least one further terminal with the identification datum of the at least one second terminal.

Abstract: A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.

Abstract: A method and system for adapting automated interactions that allows the interactive behavior of an automated system, or the nature of the interaction elements implemented thereon, to be adapted to properties and/or behaviors of users of such systems in order to enhance operating convenience. Interaction adaptation is performed with reference to user groups to which the users are allocated.

Abstract: Network power fault detection. At least one first network device is instructed to temporarily disconnect from a power supply path of a network, and at least one characteristic of the power supply path of the network is measured at a second network device connected to the network while the at least one first network device is temporarily disconnected from the network.

Abstract: A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads.