Patents by Inventor Masachika Masuda
Masachika Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9870983Abstract: A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the plurality of lead portions are arranged in an alternately staggered form such that the respective external terminals of a pair of lead portions adjacent to each other are alternatively located on an inside or an outside. A lead portion has an inside region located on the inside of a first external terminal, an outside region located on the outside of the first external terminal, and an external terminal region having the first external terminal. The inside region and the outside region are each formed thin by means of half etching. A maximum thickness of the outside region is larger than a maximum thickness of the inside region.Type: GrantFiled: November 29, 2016Date of Patent: January 16, 2018Assignee: DAI NIPPON PRINTING CO., LTD.Inventors: Satoshi Shibasaki, Koji Tomita, Masaki Yazaki, Kazuyuki Miyano, Atsushi Kurahashi, Kazuhito Uchiumi, Masachika Masuda
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Publication number: 20170077011Abstract: A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the plurality of lead portions are arranged in an alternately staggered form such that the respective external terminals of a pair of lead portions adjacent to each other are alternatively located on an inside or an outside. A lead portion has an inside region located on the inside of a first external terminal, an outside region located on the outside of the first external terminal, and an external terminal region having the first external terminal. The inside region and the outside region are each formed thin by means of half etching. A maximum thickness of the outside region is larger than a maximum thickness of the inside region.Type: ApplicationFiled: November 29, 2016Publication date: March 16, 2017Applicant: DAI NIPPON PRINTING CO., LTD.Inventors: Satoshi SHIBASAKI, Koji TOMITA, Masaki YAZAKI, Kazuyuki MIYANO, Atsushi KURAHASHI, Kazuhito UCHIUMI, Masachika MASUDA
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Patent number: 9543169Abstract: A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the plurality of lead portions are arranged in an alternately staggered form such that the respective external terminals of a pair of lead portions adjacent to each other are alternatively located on an inside or an outside. A lead portion has an inside region located on the inside of a first external terminal, an outside region located on the outside of the first external terminal, and an external terminal region having the first external terminal. The inside region and the outside region are each formed thin by means of half etching. A maximum thickness of the outside region is larger than a maximum thickness of the inside region.Type: GrantFiled: January 8, 2016Date of Patent: January 10, 2017Assignee: DAI NIPPON PRINTING CO., LTD.Inventors: Satoshi Shibasaki, Koji Tomita, Masaki Yazaki, Kazuyuki Miyano, Atsushi Kurahashi, Kazuhito Uchiumi, Masachika Masuda
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Publication number: 20160189978Abstract: A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the plurality of lead portions are arranged in an alternately staggered form such that the respective external terminals of a pair of lead portions adjacent to each other are alternatively located on an inside or an outside. A lead portion has an inside region located on the inside of a first external terminal, an outside region located on the outside of the first external terminal, and an external terminal region having the first external terminal. The inside region and the outside region are each formed thin by means of half etching. A maximum thickness of the outside region is larger than a maximum thickness of the inside region.Type: ApplicationFiled: January 8, 2016Publication date: June 30, 2016Applicant: DAI NIPPON PRINTING CO., LTD.Inventors: Satoshi SHIBASAKI, Koji TOMITA, Masaki YAZAKI, Kazuyuki MIYANO, Atsushi KURAHASHI, Kazuhito UCHIUMI, Masachika MASUDA
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Patent number: 9324636Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal.Type: GrantFiled: June 23, 2014Date of Patent: April 26, 2016Assignee: DAI NIPPON PRINTING CO., LTD.Inventors: Susumu Baba, Masachika Masuda, Hiromichi Suzuki
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Patent number: 9263374Abstract: A semiconductor device includes, a lead frame having a die pad and a plurality of leads each disposed around the die pad, a semiconductor element rested on the die pad of the lead frame, and bonding wires for electrically interconnecting the lead of the lead frame and the semiconductor element. The lead frame, the semiconductor element, and the bonding wires are sealed with a sealing resin section. The sealing resin section includes a central region provided over and around the semiconductor device, and a marginal region provided in the periphery of the central region. Thickness of the central region is greater than that of the marginal region.Type: GrantFiled: September 12, 2011Date of Patent: February 16, 2016Assignee: DAI NIPPON PRINTING CO., LTD.Inventors: Masachika Masuda, Koji Tomita, Tadashi Okamoto, Yasunori Tanaka, Hiroshi Ohsawa, Kazuyuki Miyano, Atsushi Kurahashi, Hiromichi Suzuki
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Patent number: 9257306Abstract: A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the plurality of lead portions are arranged in an alternately staggered form such that the respective external terminals of a pair of lead portions adjacent to each other are alternatively located on an inside or an outside. A lead portion has an inside region located on the inside of a first external terminal, an outside region located on the outside of the first external terminal, and an external terminal region having the first external terminal. The inside region and the outside region are each formed thin by means of half etching. A maximum thickness of the outside region is larger than a maximum thickness of the inside region.Type: GrantFiled: April 16, 2014Date of Patent: February 9, 2016Assignee: DAI NIPPON PRINTING CO., LTD.Inventors: Satoshi Shibasaki, Koji Tomita, Masaki Yazaki, Kazuyuki Miyano, Atsushi Kurahashi, Kazuhito Uchiumi, Masachika Masuda
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Patent number: 9159706Abstract: A device featuring a substrate configured to include an upper surface and an opposing lower surface and, in parallel, a first and an opposing second peripheral edge, the first peripheral edge being smaller in length than the second peripheral edge, one or more semiconductor chip mounted over the upper surface of the substrate, a control semiconductor chip mounted over the upper surface of the substrate, a sealing resin covering the memory and control chips, and a plurality of external terminals provided over the lower surface of the substrate, the external terminals being arranged in a line along the first peripheral edge. The external terminals are used to fit the device to an electronic apparatus. The device may be a memory card having a stacked arrangement of two or more memory chips, and with the control chip being apart from or included in the stacked arrangement.Type: GrantFiled: September 17, 2014Date of Patent: October 13, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Masachika Masuda, Toshihiko Usami
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Publication number: 20150001538Abstract: A device featuring a substrate configured to include an upper surface and an opposing lower surface and, in parallel, a first and an opposing second peripheral edge, the first peripheral edge being smaller in length than the second peripheral edge, one or more semiconductor chip mounted over the upper surface of the substrate, a control semiconductor chip mounted over the upper surface of the substrate, a sealing resin covering the memory and control chips, and a plurality of external terminals provided over the lower surface of the substrate, the external terminals being arranged in a line along the first peripheral edge. The external terminals are used to fit the device to an electronic apparatus. The device may be a memory card having a stacked arrangement of two or more memory chips, and with the control chip being apart from or included in the stacked arrangement.Type: ApplicationFiled: September 17, 2014Publication date: January 1, 2015Inventors: Masachika Masuda, Toshihiko Usami
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Publication number: 20140319663Abstract: A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the plurality of lead portions are arranged in an alternately staggered form such that the respective external terminals of a pair of lead portions adjacent to each other are alternatively located on an inside or an outside. A lead portion has an inside region located on the inside of a first external terminal, an outside region located on the outside of the first external terminal, and an external terminal region having the first external terminal. The inside region and the outside region are each formed thin by means of half etching. A maximum thickness of the outside region is larger than a maximum thickness of the inside region.Type: ApplicationFiled: April 16, 2014Publication date: October 30, 2014Inventors: Satoshi SHIBASAKI, Koji TOMITA, Masaki YAZAKI, Kazuyuki MIYANO, Atsushi KURAHASHI, Kazuhito UCHIUMI, Masachika MASUDA
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Publication number: 20140299995Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal.Type: ApplicationFiled: June 23, 2014Publication date: October 9, 2014Applicant: Dai Nippon Printing Co., Ltd.Inventors: Susumu BABA, Masachika MASUDA, Hiromichi SUZUKI
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Patent number: 8853864Abstract: A device featuring a substrate configured to include an upper surface and an opposing lower surface and, in parallel, a first and an opposing second peripheral edge, the first peripheral edge being smaller in length than the second peripheral edge, one or more semiconductor chip mounted over the upper surface of the substrate, a control semiconductor chip mounted over the upper surface of the substrate, a sealing resin covering the memory and control chips, and a plurality of external terminals provided over the lower surface of the substrate, the external terminals being arranged in a line along the first peripheral edge. The external terminals are used to fit the device to an electronic apparatus. The device may be a memory card having a stacked arrangement of two or more memory chips, and with the control chip being apart from or included in the stacked arrangement.Type: GrantFiled: July 25, 2013Date of Patent: October 7, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Masachika Masuda, Toshihiko Usami
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Patent number: 8796832Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal.Type: GrantFiled: February 23, 2012Date of Patent: August 5, 2014Assignee: Dai Nippon Printing Co., Ltd.Inventors: Susumu Baba, Masachika Masuda, Hiromichi Suzuki
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Patent number: 8742554Abstract: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.Type: GrantFiled: April 26, 2006Date of Patent: June 3, 2014Assignee: Dai Nippon Printing Co., Ltd.Inventors: Yo Shimazaki, Hiroyuki Saito, Masachika Masuda, Kenji Matsumura, Masaru Fukuchi, Takao Ikezawa
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Patent number: 8739401Abstract: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.Type: GrantFiled: September 9, 2010Date of Patent: June 3, 2014Assignee: Dai Nippon Printing Co., Ltd.Inventors: Yo Shimazaki, Hiroyuki Saito, Masachika Masuda, Kenji Matsumura, Masaru Fukuchi, Takao Ikezawa
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Patent number: 8653647Abstract: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.Type: GrantFiled: June 30, 2010Date of Patent: February 18, 2014Assignee: Dai Nippon Printing Co., Ltd.Inventors: Masachika Masuda, Chikao Ikenaga
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Publication number: 20130328046Abstract: A device featuring a substrate configured to include an upper surface and an opposing lower surface and, in parallel, a first and an opposing second peripheral edge, the first peripheral edge being smaller in length than the second peripheral edge, one or more semiconductor chip mounted over the upper surface of the substrate, a control semiconductor chip mounted over the upper surface of the substrate, a sealing resin covering the memory and control chips, and a plurality of external terminals provided over the lower surface of the substrate, the external terminals being arranged in a line along the first peripheral edge. The external terminals are used to fit the device to an electronic apparatus. The device may be a memory card having a stacked arrangement of two or more memory chips, and with the control chip being apart from or included in the stacked arrangement.Type: ApplicationFiled: July 25, 2013Publication date: December 12, 2013Applicant: Elpida Memory, Inc.Inventors: Masachika MASUDA, Toshihiko USAMI
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Patent number: 8502395Abstract: A semiconductor device featuring a substrate having a first surface defined by a first edge and an opposing second edge, electrode pads formed on the first surface, a first semiconductor chip mounted over the first surface between the first edge and the electrode pads and including first pads each electrically connected to a corresponding electrode pad, a second semiconductor chip stacked over the first semiconductor chip and including second pads each electrically connected to a corresponding electrode pad, a third semiconductor chip mounted over the first surface of the substrate between the second edge and the electrode pads and including third pads each electrically connected to a corresponding electrode pad, in which one electrode pad is electrically connected to one first pad, one second pad and one third pad and another electrode pad is electrically connected to a first pad and a second pad corresponding thereto, via separate bonding wires.Type: GrantFiled: March 7, 2012Date of Patent: August 6, 2013Assignee: Elpida Memory, Inc.Inventors: Masachika Masuda, Toshihiko Usami
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Patent number: 8471371Abstract: A semiconductor composite wiring assembly includes a wiring assembly and a lead frame. A copper wiring layer of the wiring assembly includes first terminals, second terminals, and wiring sections connecting the terminals. The second terminals and the lead frame are electrically connected by connecting members. The lead frame includes a die pad for mounting the wiring assembly, and lead sections located at outer positions. The die pad includes a central area in which a semiconductor chip is mounted via the wiring assembly, and a peripheral area connected to the central area with spaces formed therebetween that serve as resin-seal inflow spaces. The wiring assembly is positioned over the central area and the peripheral area so as to cover the central area completely and the peripheral area partially, and at least the central area and the peripheral area of the die pad are glued to the wiring assembly by resin paste.Type: GrantFiled: February 5, 2010Date of Patent: June 25, 2013Assignee: Dai Nippon Printing Co., Ltd.Inventors: Susumu Baba, Masachika Masuda, Hiromichi Suzuki
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Patent number: RE45931Abstract: For the manufacturing of semiconductor devices, in which multiple semiconductor chips which are mounted on a wiring substrate are processed for block molding and thereafter the wiring substrate is diced into individual resin-molded semiconductor devices, disclosed herein is a technique for easily determining the position of each resin-molded semiconductor device in its former state on the wiring substrate even after the dicing process. The processing steps include implementing the block molding with resin for multiple semiconductor chips mounted on a wiring substrate and thereafter dicing the wiring substrate into individual resin-molded semiconductor devices, with the substrate dicing step being preceded by a step of appending an address information pattern to each of the resin-molded semiconductor devices.Type: GrantFiled: May 30, 2014Date of Patent: March 15, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tsutomu Wada, Masachika Masuda