Patents by Inventor Masachika Masuda

Masachika Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090189263
    Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device electrically connects an electrode provided on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The metal substrate is provided on one side of the insulating layer. The copper wiring layer is provided on another side of the insulating layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode provided on the semiconductor chip. The second terminal is connected with the external wiring device.
    Type: Application
    Filed: January 13, 2009
    Publication date: July 30, 2009
    Applicant: DAI NIPPON PRINTING CO., LTD.
    Inventors: Susumu Baba, Masachika Masuda, Hiromichi Suzuki
  • Publication number: 20090146280
    Abstract: A circuit member 20 includes a lead frame material 1 having a die pad 3, a lead part 6 to be electrically connected with a semiconductor chip 30, and an outer frame 2 configured to support the die pad and the lead part. The lead frame material includes a resin sealing region 9. Roughened faces 10A to 10C and 11A to 11C, each having an average roughness Ra of 0.3 ?m or greater, are formed on a surface in the resin sealing region of the lead frame material. The surface of the lead frame material except for the resin sealing region is a flat and smooth face. A two-layer plated layer 12A formed by laminating a Ni plated layer 13 and a Pd plated layer 14 in this order or a three-layer plated layer 12B formed by laminating the Ni plated layer 13, the Pd plated layer 14 and an Au plated layer 15 in this order is formed on the whole surface of the lead frame material.
    Type: Application
    Filed: November 28, 2006
    Publication date: June 11, 2009
    Applicant: Dai Nippon Printing Co., Ltd.
    Inventors: Yo Shimazaki, Hiroyuki Saito, Masachika Masuda, Kenji Matsumura, Masaru Fukuchi, Takao Ikezawa
  • Publication number: 20090140411
    Abstract: The present invention provides a resin-sealed semiconductor device, which includes a semiconductor element; a plurality of terminal members, each surrounding the semiconductor element and including an external terminal portion, an internal terminal portion and a connecting portion; bonding wires, each connecting the semiconductor element with the internal terminal portion; and a resin-sealing portion sealing the semiconductor element, terminal members and bonding wires. Each terminal member is composed of an inner thinned portion forming the internal terminal portion and an outer thickened portion forming the external terminal portion. A rear face of each internal terminal portion, and a front face, a rear face and an outer side face of each external terminal portion are exposed to the outside from the resin-sealing portion, respectively.
    Type: Application
    Filed: June 22, 2007
    Publication date: June 4, 2009
    Applicant: Dai Nappon Printing Co., Ltd
    Inventors: Masachika Masuda, Chikao Ikenaga, Koji Tomita
  • Publication number: 20090039486
    Abstract: A circuit member includes a frame substrate formed, by patterning a rolled copper plate or a rolled copper alloy plate, with a die pad portion for a semiconductor chip to be mounted thereon, and a lead portion for an electrical connection to the semiconductor chip, having rough surfaces formed as roughed surfaces on upsides and lateral wall sides of the die pad portion and the lead portion, and smooth surfaces formed on downsides of the die pad portion and the lead portion, and the die pad portion and the lead portion are buried in a sealing resin, having a downside of the lead portion exposed.
    Type: Application
    Filed: April 26, 2006
    Publication date: February 12, 2009
    Inventors: Yo Shimazaki, Hiroyuki Saito, Masachika Masuda, Kenji Matsumura, Masaru Fukuchi, Takao Ikezawa
  • Publication number: 20080290488
    Abstract: Detachably mountable memory card featuring a memory chip(s) and a control chip includes a substrate of an insulating material, conductive layers provided on a first main surface of the substrate, a plurality of external electrode terminals exposed to the opposing, second main surface of the substrate, and conductive portions electrically connecting the conductive layers with corresponding ones of the external electrode terminals. The memory chip(s) and the control chip are electrically connected with ones of the conductive layers. The memory card also includes an encapsulating insulating layer covering the first main surface of the substrate, the fixedly disposed memory and control chips thereon, and the conductive layers, the encapsulating insulating layer having an exposed flat surface representing one main plane surface of the finished memory card, and the second main surface of the substrate representing another main plane surface of the memory card with the exposed external electrode terminals.
    Type: Application
    Filed: February 19, 2008
    Publication date: November 27, 2008
    Inventors: Masachika Masuda, Toshihiko Usami
  • Publication number: 20080251902
    Abstract: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.
    Type: Application
    Filed: June 17, 2008
    Publication date: October 16, 2008
    Applicant: Dai Nippon Printing Co., Ltd.
    Inventors: Masachika Masuda, Chikao Ikenaga
  • Patent number: 7405468
    Abstract: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: July 29, 2008
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Masachika Masuda, Chikao Ikenaga
  • Patent number: 7365441
    Abstract: A semiconductor device fabricating method comprises a substrate forming step of forming a plurality of separate conductive pads 20 on an adhesive layer included in an adhesive sheet 50, and a semiconductor chip mounting step of bonding semiconductor chips to the adhesive sheet 50 with surfaces thereof not provided with any electrodes in contact with the adhesive sheet 50, and electrically connecting electrodes 11 formed on the semiconductor chips 10 and upper parts of the conductive pads 20 with wires 30. The semiconductor chips 10, the wires 30 and the conductive pads 20 are sealed in a sealing resin molding 40, and then the adhesive sheet 50 is separated from the sealing resin molding 40. Each of the conductive pads 20 has a reduced part 20b, and a jutting part 20a jutting out from the reduced part 20b. The conductive pads 20 having such construction can be firmly bonded to the sealing resin molding 40.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: April 29, 2008
    Assignees: Dai Nippon Printing Co., Ltd., Nitto Denko Corporation
    Inventors: Chikao Ikenaga, You Shimazaki, Masachika Masuda, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura
  • Patent number: 7348668
    Abstract: A memory card containing a resin sealed stacking of plural semiconductor chips which are rear surface mounted over a main surface of a base substrate, the rear surface of the substrate being provided with external connection terminals. The relatively lower ones of the stacked semiconductor chips include a memory circuit and may be larger in size than the uppermost chip which contains a control circuit. Resin sealed wiring connections between bonding pads on the main surface of the respective chips and corresponding ones of electrodes on the main surface of the substrate are arranged so as to avoid crossovers between them, with respect to a plan view thereof. A resin cap may be used to cover the main surface side of the base substrate, which has the resin sealed semiconductor chips mounted thereon.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: March 25, 2008
    Assignee: Elpida Memory, Inc.
    Inventors: Masachika Masuda, Toshihiko Usami
  • Patent number: 7294918
    Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: November 13, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Tamaki Wada, Hirotaka Nishizawa, Masachika Masuda, Kenji Osawa, Junichiro Osako, Satoshi Hatakeyama, Haruji Ishihara, Kazuo Yoshizaki, Kazunori Furusawa
  • Patent number: 7271471
    Abstract: A metal substrate apparatus comprises a plurality of metal substrates forming an IC card module used in manufacturing transfer mold-type non-contact IC cards. The metal substrate apparatus comprises a thin metal strip of processing material, and each metal substrate has connecting parts. Each metal substrate has a die pad for loading an IC chip. Antenna terminals to connect antenna coils are located outside the die pad and a resin-sealed region. The antenna terminals of one metal substrate and those of a longitudinally adjacent metal substrate overlap a shared region of the processing material in a width direction. The metal substrates can be separated by sealing and then making longitudinal cuts on the processing material on the outer parts of the metal substrates along two connecting lines.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: September 18, 2007
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Masachika Masuda, Chikao Ikenaga
  • Patent number: 7271475
    Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: September 18, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Tamaki Wada, Hirotaka Nishizawa, Masachika Masuda, Kenji Osawa, Junichiro Osako, Satoshi Hatakeyama, Haruji Ishihara, Kazuo Yoshizaki, Kazunori Furusawa
  • Patent number: 7239011
    Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: July 3, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Tamaki Wada, Hirotaka Nishizawa, Masachika Masuda, Kenji Osawa, Junichiro Osako, Satoshi Hatakeyama, Haruji Ishihara, Kazuo Yoshizaki, Kazunori Furusawa
  • Patent number: 7233058
    Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: June 19, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Tamaki Wada, Hirotaka Nishizawa, Masachika Masuda, Kenji Osawa, Junichiro Osako, Satoshi Hatakeyama, Haruji Ishihara, Kazuo Yoshizaki, Kazunori Furusawa
  • Patent number: 7227251
    Abstract: A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: June 5, 2007
    Assignee: Elpida Memory, Inc.
    Inventors: Kazuki Sakuma, Masayasu Kawamura, Yasushi Takahashi, Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano
  • Patent number: 7122883
    Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: October 17, 2006
    Assignees: Hitachi, Ltd., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura
  • Publication number: 20060220204
    Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.
    Type: Application
    Filed: May 10, 2006
    Publication date: October 5, 2006
    Inventors: Tamaki Wada, Hirotaka Nishizawa, Masachika Masuda, Kenji Osawa, Junichiro Osako, Satoshi Hatakeyama, Haruji Ishihara, Kazuo Yoshizaki, Kazunori Furusawa
  • Publication number: 20060220203
    Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.
    Type: Application
    Filed: May 10, 2006
    Publication date: October 5, 2006
    Inventors: Tamaki Wada, Hirotaka Nishizawa, Masachika Masuda, Kenji Osawa, Junichiro Osako, Satoshi Hatakeyama, Haruji Ishihara, Kazuo Yoshizaki, Kazunori Furusawa
  • Publication number: 20060170084
    Abstract: A memory card containing a resin sealed stacking of plural semiconductor chips which are rear surface mounted over a main surface of a base substrate, the rear surface of the substrate being provided with external connection terminals. The relatively lower ones of the stacked semiconductor chips include a memory circuit and may be larger in size than the uppermost chip which contains a control circuit. Resin sealed wiring connections between bonding pads on the main surface of the respective chips and corresponding ones of electrodes on the main surface of the substrate are arranged so as to avoid crossovers between them, with respect to a plan view thereof. A resin cap may be used to cover the main surface side of the base substrate, which has the resin sealed semiconductor chips mounted thereon.
    Type: Application
    Filed: March 30, 2006
    Publication date: August 3, 2006
    Inventors: Masachika Masuda, Toshihiko Usami
  • Publication number: 20060145363
    Abstract: A semiconductor device fabricating method comprises a substrate forming step of forming a plurality of separate conductive pads 20 on an adhesive layer included in an adhesive sheet 50, and a semiconductor chip mounting step of bonding semiconductor chips to the adhesive sheet 50 with surfaces thereof not provided with any electrodes in contact with the adhesive sheet 50, and electrically connecting electrodes 11 formed on the semiconductor chips 10 and upper parts of the conductive pads 20 with wires 30. The semiconductor chips 10, the wires 30 and the conductive pads 20 are sealed in a sealing resin molding 40, and then the adhesive sheet 50 is separated from the sealing resin molding 40. Each of the conductive pads 20 has a reduced part 20b, and a jutting part 20a jutting out from the reduced part 20b. The conductive pads 20 having such construction can be firmly bonded to the sealing resin molding 40.
    Type: Application
    Filed: February 28, 2006
    Publication date: July 6, 2006
    Applicants: DAI NIPPON PRINTING CO., LTD., NITTO DENKO CORPORATION
    Inventors: Chikao Ikenaga, You Shimazaki, Masachika Masuda, Kazuhito Hosokawa, Takuji Okeyui, Keisuke Yoshikawa, Kazuhiro Ikemura