Method of manufacturing a semiconductor device
For the manufacturing of semiconductor devices, in which multiple semiconductor chips which are mounted on a wiring substrate are processed for block molding and thereafter the wiring substrate is diced into individual resin-molded semiconductor devices, disclosed herein is a technique for easily determining the position of each resin-molded semiconductor device in its former state on the wiring substrate even after the dicing process. The processing steps include implementing the block molding with resin for multiple semiconductor chips mounted on a wiring substrate and thereafter dicing the wiring substrate into individual resin-molded semiconductor devices, with the substrate dicing step being preceded by a step of appending an address information pattern to each of the resin-molded semiconductor devices.
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The present invention relates to the technology of the manufacturing of semiconductor devices, and particularly to a technique which is useful for the manufacturing of semiconductor devices of the resin mold type in which multiple semiconductor chips mounted on a wiring substrate are processed for block molding and thereafter the wiring substrate is diced into individual semiconductor devices.
Japanese Patent Unexamined Publication No. Hei 11(1999)-214588 describes a method of manufacturing semiconductor devices of the resin mold type in which multiple semiconductor chips mounted on a TAB tape are molded with resin and thereafter the resin and TAB tape are cut into individual semiconductor devices.
The above-mentioned patent publication also discloses a technique for preventing the displacement of the cutting position of the resin and TAB tape based on the accurate observation of the cutting position which is displayed in terms of the reflected light from part of copper wire patterns formed in the periphery of the land section of the resin-molded tape.
SUMMARY OF THE INVENTIONThe inventors of the present invention are developing a technique for manufacturing semiconductor devices of the resin mold type in which multiple semiconductor chips which are mounted in a matrix arrangement on a wiring substrate are processed for block molding and thereafter the wiring substrate is diced into individual semiconductor devices.
In adopting this manufacturing method, it is necessary to know easily, even after the dicing process, the position of each finished resin-molded semiconductor device in its former state on the wiring substrate in order to conduct the prompt analysis of faulty products resulting from a process and find out the defective position.
A conceivable manner, for example, is to form marks of address information on the injector pin or the like of the molding die which is used for molding semiconductor chips with resin so that distinct address information is appended to the area of each resin-molded semiconductor device at the block molding of semiconductor chips on the wiring substrate.
However, this manner necessitates an awkward work of forming on the molding die different patterns of address information for each type of product, and it is not applicable to the case of using standard (existing) molding dies of clients.
It is an object of the present invention to provide for the manufacturing of semiconductor devices of the resin mold type, in which multiple semiconductor chips which are mounted on a wiring substrate are processed for block molding and thereafter the wiring substrate is diced into multiple semiconductor devices, a technique for finding out easily, even after the dicing process, the position of each resin-molded semiconductor device in its former state on the wiring substrate.
These and other objects and novel features of the present invention will become apparent from the following description of specification taken in conjunction with the accompanying drawings.
Among the affairs of the present invention disclosed in this specification, representatives are summarized as follows.
The inventive method of manufacturing semiconductor devices includes processing steps of implementing the block molding with resin for a plurality of semiconductor chips which are mounted on a wiring substrate and thereafter dicing the wiring substrate into a plurality of resin-molded semiconductor devices, with the substrate dicing step being preceded by a step of appending address information to each of the resin-molded semiconductor devices.
The inventive method of manufacturing semiconductor devices includes processing steps of implementing the block molding with resin for a plurality of semiconductor chips which are mounted on a wiring substrate and thereafter dicing the wiring substrate into a plurality of resin-molded semiconductor devices, with the substrate dicing step being preceded by a step of appending address information of each of the resin-molded semiconductor devices to part of the wiring substrate.
The inventive method of manufacturing semiconductor devices includes processing steps of implementing the block molding with resin for a plurality of semiconductor chips which are mounted on a wiring substrate and thereafter dicing the wiring substrate into a plurality of resin-molded semiconductor devices, with the substrate dicing step being preceded by a step of appending address information of each of the resin-molded semiconductor devices to part of the resin mold corresponding to the individual resin-molded semiconductor devices.
The inventive method of manufacturing semiconductor devices includes processing steps of dividing semiconductor chips which are mounted on a wiring substrate into blocks and molding the chips with resin and thereafter dicing each of the blocks into a plurality of resin-molded semiconductor devices.
Embodiments of this invention will be explained in detail with reference to the drawings. Throughout the drawings which explain the embodiments, identical parts are referred to by the same symbols, and their explanation will not be repeated.
Embodiment 1The matrix substrate 1A is a thin wiring substrate of resin having dimensions of 500 mm by 500 mm and 0.22 to 0.6 mm in thickness, for example, on the upper side of which are mounted a plurality of semiconductor chips in a matrix arrangement in the pellet putting process which will be explained later. The matrix substrate 1A is made of a known material for wiring substrates, e.g., glass epoxy resin, BT resin or polyamide resin, and particularly it can be made of such an inexpensive material for wiring substrates as glass epoxy resin thereby to lower the manufacturing cost of resin-molded semiconductor devices. The matrix substrate 1A can also be made of a wiring substrate having flexibility such as a flexible printed circuit (FPC) for example.
As shown in
As shown in
The number of pads 4 formed in the area of one resin-molded semiconductor device is 6 by 8 in the longitudinal and lateral directions, i.e., 48, for example. The pads 4 have an interval of alignment of 0.75 mm in the longitudinal and lateral directions for example. The alignment target 6 and index pattern 7 shown in the figure have a cross and triangular shapes, respectively, for example.
The address information pattern 8 contains information indicative of the position of the resin-molded semiconductor device within the matrix substrate 1A. Specifically, areas of individual semiconductor devices have patterns of are A11, A12, . . . , A21, A22, . . . , and so on. The alignment target 6, index pattern 7 and address information pattern 8 located at separate positions in the example shown in the figure can be unified and located at one position to have these roles at once. For example,
The address information pattern 8, which is a 3-digit character pattern such as A11, A12, . . . , A21, A22, . . . , and so on in the example shown in the figure, can be arbitrary provided that it is unique to each area of one resin-molded semiconductor device. The address information pattern 8 may contain information other than the chip location of the foregoing case, e.g., it may contain the production lot or the type number of the molding die which is used in the molding process which will be explained later.
Next, the method of manufacturing resin-molded semiconductor devices based on the foregoing matrix substrate 1A will be explained by following the processing steps in connection with
Initially, the matrix substrate 1A is cut into segments to get matrix substrates 1B for molding as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Due to the larger size of the matrix substrate 1B as compared with usual resin-molded semiconductor devices (e.g., QFP), the contraction of the resin mold 14 following the block molding of all chips 12 on the matrix substrate 1B can cause it to warp, resulting possibly in the difficulty of connection between pads 4 and solder bumps in the ball bonding process which will be explained later. Therefore, if this event is probable, it is desirable to prevent the warping of matrix substrate 1B by using a molding die having multiple cavities thereby to split the substrate 1B into multiple blocks, or forming slits 16 in the matrix substrate 1B as shown in
Next, as shown in
Next, as shown in
The resin-molded semiconductor devices 20 resulting from the dicing of the matrix substrate 1B undergo the selection test with testers, and a mark 19 of the product type, lot number, etc. (including the index mark of the upper side) is printed on the surface of the resin mold 14 as shown in
The resin-molded semiconductor devices 20 undergo the selection test with testers and visual inspection, and selected good products are packed and shipped to the client manufacturer, where these parts will be packaged on circuit boards of various electronic appliances. At the mounting of a resin-molded semiconductor device 20 on a circuit board, it is positioned accurately based on the observation of the index pattern 7 formed on its packaging surface with a camera or the like.
According to the manufacturing method of the foregoing embodiment, it is readily possible, even after the dicing of matrix substrate 1A, to find out the position of each finished resin-molded semiconductor device 20 in its former state on the matrix substrate 1A based on the observation with a camera, microscope, or human eyes of the address information pattern 8 which has been formed on the matrix substrate 1A, whereby the analysis of faulty products resulting from a process and finding of the defective position can be done promptly.
Embodiment 2The address information patterns 8, which are formed by use of the wiring material on the packaging surface of the matrix substrate 1A in the preceding embodiment 1, can be formed in a different manner as follows.
Initially, a matrix substrate 1A as shown in
Next, the processing steps of the preceding embodiment 1 shown in
Next, the processing steps of the preceding embodiment 1 shown in
The present invention has been explained for its specific embodiments, however, the invention is not confined to these embodiments, but can be altered obviously in various ways without departing from the essence of the invention.
The present invention is not confined to resin-molded semiconductor devices of the BGA type, but is applicable to various resin-molded semiconductor devices, such as TSOJ, LGA and mini-card, having external connecting terminals other than the solder bumps. Semiconductor chips are not confined to SRAM, but various memory LSI chips such as of DRAM and flash memory can be used.
The effectiveness achieved by the representative affairs of invention disclosed in this specification is summarized as follows.
Based on the present invention for the manufacturing of resin-molded semiconductor devices, in which multiple semiconductor chips which are mounted on a wiring substrate are processed for block molding and thereafter the wiring substrate is diced into multiple semiconductor devices, it becomes possible, even after the dicing process, to find out the position of each finished resin-molded semiconductor device in its former state on the wiring substrate, whereby the analysis of faulty products resulting from a process and finding of the defective position can be done promptly.
The inventive technique is applicable also to the case of using standard (existing) molding dies of clients, whereby the manufacturing cost of resin-molded semiconductor devices can be reduced.
Claims
1. A method of manufacturing a semiconductor device including processing steps of implementing the block molding with resin for a plurality of semiconductor chips which are mounted on a wiring substrate and thereafter dicing the wiring substrate into a plurality of resin-molded semiconductor devices,
- wherein said method further includes a step, which precedes said substrate dicing step, of appending address information to each of the resin-molded semiconductor devices.
2. A method of manufacturing a semiconductor device according to claim 1 including processing steps of implementing the block molding with resin for a plurality of semiconductor chips which are mounted on a wiring substrate and thereafter dicing the wiring substrate into a plurality of resin-molded semiconductor devices,
- wherein said method further includes a step, which precedes said substrate dicing step, of appending address information to each of the resin-molded semiconductor devices, and
- wherein said address information includes information indicative of the position of each of the resin-molded semiconductor devices within the wiring substrate.
3. A method of manufacturing a semiconductor device including processing steps of implementing the block molding with resin for a plurality of semiconductor chips which are mounted on a wiring substrate and thereafter dicing the wiring substrate into a plurality of resin-molded semiconductor devices,
- wherein said method further includes a step, which precedes said substrate dicing step, of appending address information of each of the resin-molded semiconductor devices to part of the wiring substrate.
4. A method of manufacturing a semiconductor device according to claim 3, wherein further including a step of forming wire patterns with a wiring material on the wiring substrate and shaping said wiring material such that said address information is shaped in a the wiring material which has been formed in a the step of forming wire patterns on the wiring substrate.
5. A method of manufacturing a semiconductor device according to claim 4, wherein said address information also has the role of index information which orients the resin-molded semiconductor device on a circuit board at packaging.
6. A method of manufacturing a semiconductor device according to claim 4, wherein said address information is shaped at a position different from the position of index information which orients the resin-molded semiconductor device on a circuit board at packaging.
7. A method of manufacturing a semiconductor device including processing steps of implementing the block molding with resin for a plurality of semiconductor chips which are mounted on a wiring substrate and thereafter dicing the wiring substrate into a plurality of resin-molded semiconductor devices,
- wherein said method further includes a step, which precedes said substrate dicing step that follows the block molding with resin of said semiconductor chips, of appending address information to each of the resin-molded semiconductor devices.
8. A method of manufacturing a semiconductor device according to claim 7, wherein said address information is shaped in a step of printing a mark on the surface of the resin mold.
9. A method of manufacturing a semiconductor device according to claim 8, wherein said address information and said mark are printed based on a laser printing scheme.
10. A method of manufacturing a semiconductor device according to claim 7, wherein said address information is shaped in a step different from a step of printing the mark on the resin mold.
11. A method of manufacturing a semiconductor device including processing steps of implementing the block molding with resin for a plurality of semiconductor chips which are mounted on a wiring substrate and thereafter dicing the wiring substrate into a plurality of resin-molded semiconductor devices,
- wherein said method further includes a step, which precedes said substrate dicing step, of appending address information of each of the resin-molded semiconductor devices to part of the wiring substrate,
- wherein the wiring substrate has an upper surface, and a lower surface opposite to the upper surface,
- wherein the semiconductor chips are mounted on the upper surface of the wiring substrate, and
- wherein the address information of each of the resin-molded semiconductor devices is appended on the lower surface of the wiring substrate.
12. The method according to claim 11,
- wherein the block molding is implemented such that the resin covers the semiconductor chips and the upper surface of the wiring substrate.
13. The method according to claim 11,
- wherein the block molding is implemented such that the resin does not cover the address information of each of the resin-molded semiconductor devices.
14. The method according to claim 11,
- wherein the block molding is implemented such that the resin avoids contacting the address information of each of the resin-molded semiconductor devices.
15. The method according to claim 11,
- wherein the block molding is implemented such that the address information of each of the resin-molded semiconductor devices is located in an area spaced apart from where the resin is located.
16. The method according to claim 11,
- further including a step of forming a plurality of pads of each of the resin-molded semiconductor devices on the lower surface of the wiring substrate.
17. The method according to claim 16,
- wherein the address information in an area of the lower surface of the wiring substrate in which the pads are not formed.
18. The method according to claim 17,
- further including a step of forming a plurality of bumps on the pads, respectively.
19. The method according to claim 16,
- wherein the address information in an area of the lower surface of the wiring substrate that is spaced apart from areas in which the pads are formed.
20. The method according to claim 19,
- further including a step of forming a plurality of bumps on the pads, respectively.
21. The method according to claim 11,
- wherein the address information is comprised of a pattern made of a copper foil.
22. The method according to claim 21,
- wherein a pattern of the address information of each of the resin-molded semiconductor devices is different from one another.
23. The method according to claim 21,
- wherein the address information is comprised of alphanumeric characters.
24. The method according to claim 21,
- further including a step of forming a plurality of pads of each of the resin-molded semiconductor devices on the lower surface of the wiring substrate, and
- wherein the pads and the address information are formed by etching the copper foil.
25. The method according to claim 11,
- further including a step of forming an index pattern of each of the resin-molded semiconductor devices on the lower surface of the wiring substrate.
26. The method according to claim 25,
- wherein the address information in an area of the lower surface of the wiring substrate in which the index pattern is not formed, and
- wherein each of the address information and the index pattern is comprised of a pattern made of a copper foil.
27. The method according to claim 26,
- further including a step of forming a solder resist on the lower surface of the wiring substrate such that the solder resist covers the address information, and such that the solder resist exposes the index pattern.
28. The method according to claim 27,
- further including a step of forming a plurality of pads of each of the resin-molded semiconductor devices on the lower surface of the wiring substrate, and
- wherein the solder resist is formed on the lower surface of the wiring substrate such that the solder resist covers the address information, and such that the solder resist exposes the index pattern and the pads.
29. The method according to claim 28,
- further including a step of forming a plurality of bumps on the pads, respectively.
30. The method according to claim 26,
- wherein the address information is comprised of alphanumeric characters.
31. The method according to claim 26,
- wherein the index pattern and the address information are formed by etching the copper foil.
32. The method according to claim 25,
- wherein the address information is formed in an area of the lower surface of the wiring substrate which is spaced apart from an area where the index pattern is formed, and
- wherein each of the address information and the index pattern is comprised of a pattern made of a copper foil.
33. The method according to claim 32,
- further including a step of forming a solder resist on the lower surface of the wiring substrate such that the solder resist covers the address information, and such that the solder resist exposes the index pattern.
34. The method according to claim 33,
- further including a step of forming a plurality of pads of each of the resin-molded semiconductor devices on the lower surface of the wiring substrate, and
- wherein the solder resist is formed on the lower surface of the wiring substrate such that the solder resist covers the address information, and such that the solder resist exposes the index pattern and the pads.
35. The method according to claim 34,
- further including a step of forming a plurality of bumps on the pads, respectively.
36. The method according to claim 32,
- wherein the address information is comprised of alphanumeric characters.
37. The method according to claim 32,
- wherein the index pattern and the address information are formed by etching the copper foil.
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Type: Grant
Filed: May 30, 2014
Date of Patent: Mar 15, 2016
Assignee: RENESAS ELECTRONICS CORPORATION (Tokyo)
Inventors: Tsutomu Wada (Higashiyamato), Masachika Masuda (Tokorozawa)
Primary Examiner: Tuan H Nguyen
Application Number: 14/291,451
International Classification: H01L 21/44 (20060101);