Patents by Inventor Masaharu Yamaji

Masaharu Yamaji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11373997
    Abstract: An HVIC is a gate driver IC that drives a three-phase inverter and includes high-potential-side regions for three phases on a single semiconductor substrate. The high-potential-side region includes an n-type region and has a potential that is fixed at a power source voltage potential through a VB contact region in the n-type region. The high-potential-side region has a high-side driving circuit that drives an upper arm element of the inverter. An interphase region between adjacent high-potential-side regions has no GND contact region and no GND contact electrode arranged therein, and has only a p-type region at a ground potential constituting a low-potential-side region. The high-potential-side region of one phase has a p?-type opening between the high-side driving circuit of thereof and the high-side driving circuit or the GND contact region of an adjacent high-potential-side region that is of another phase and sandwiches the interphase region therebetween.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: June 28, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu Yamaji
  • Publication number: 20220190107
    Abstract: A semiconductor device includes: a well region of a second conductivity-type deposited on a surface layer of a semiconductor layer of a first conductivity-type; a breakdown voltage region of the second conductivity-type arranged to surround the well region and having a lower impurity concentration than the well region; a base region of the first conductivity-type arranged to surround the breakdown voltage region; a carrier supply region of the second conductivity-type arranged on a surface layer of the base region and serving as a level shifter; and a carrier reception region of the level shifter, wherein the carrier reception region is formed of a first universal contact region including a region of the first conductivity-type and a region of the second conductivity-type arranged in contact with each other.
    Type: Application
    Filed: October 27, 2021
    Publication date: June 16, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu YAMAJI
  • Patent number: 11233052
    Abstract: A method of manufacturing a semiconductor integrated circuit includes a first ion implantation process implanting impurity ions of a second conductivity type into a bottom surface of a semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a first current suppression layer, and a second ion implantation process implanting impurity ions of a first conductivity type into the bottom surface of the semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a second current suppression layer. The semiconductor integrated circuit includes a first well region of the first conductivity type and a second well region of the second conductivity type provided in an upper portion of the first well region. The first current suppression layer is separated from the first well region and the second current suppression layer is provided under the first current suppression layer.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: January 25, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Kanno, Masaharu Yamaji, Hitoshi Sumida
  • Publication number: 20220013466
    Abstract: A semiconductor device includes: a wiring layer; a titanium nitride layer deposited on the wiring layer; a titanium oxynitride layer deposited on the titanium nitride layer; a titanium oxide layer deposited on the titanium oxynitride layer; and a surface passivation film deposited on the titanium oxide layer, wherein an opening penetrating the titanium nitride layer, the titanium oxynitride layer, the titanium oxide layer, and the surface passivation film is provided to expose a part of the wiring layer so as to serve as a pad.
    Type: Application
    Filed: September 23, 2021
    Publication date: January 13, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Masaharu YAMAJI, Taichi KARINO, Hitoshi SUMIDA, Hideaki ITOH
  • Patent number: 11189685
    Abstract: Provided is a resistance element, including: a semiconductor substrate; a first insulating film stacked on the semiconductor substrate; a resistance layer selectively stacked on the first insulating film; a first auxiliary film separated from the resistance layer; a second auxiliary film separated from the resistance layer in a direction different from that of the first auxiliary film; a second insulating film stacked on the first insulating film to cover the resistance layer, and the first auxiliary film and the second auxiliary film; a first electrode connected to the resistance layer and stacked on the second insulating film disposed on an upper side of the first auxiliary film; and a second electrode connected to the resistance layer by being separated from the first electrode and stacked on the second insulating film on the upper side of the second auxiliary film.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masaru Saito, Masaharu Yamaji, Osamu Sasaki, Hitoshi Sumida
  • Patent number: 11171201
    Abstract: A semiconductor integrated circuit includes: a semiconductor base body of a first conductivity type; a first well region of a second conductivity type, deposited at an upper portion of the semiconductor base body, to which a first potential is applied; a second well region of the first conductivity type, deposited at an upper portion of the first well region, to which a second potential lower than the first potential is applied; a main electrode region to which the second potential is applied, the main electrode region being deposited at the upper portion of the first well region and away from the second well region; a first buried layer of the second conductivity type buried locally under the second well region; and a second buried layer of the second conductivity type buried locally under the main electrode region and away from the first buried layer.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: November 9, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu Yamaji
  • Patent number: 11146268
    Abstract: In a level shifter circuit that transmits a set signal and a reset signal input to input terminals of a high-side latch circuit, the source sides of high voltage transistors are connected to current negative feedback resistors, and transistors are connected in parallel to the current negative feedback resistors. Further included is a high-side voltage detection circuit that detects whether the voltage of a high-side power supply terminal is a high voltage. When a high voltage is detected, the transistors are turned OFF to make the drain currents that flow smaller, thereby making it possible to improve the trade-off between heat generation and propagation delay characteristics in the high voltage transistors.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: October 12, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu Yamaji
  • Publication number: 20210013203
    Abstract: A method of manufacturing a semiconductor integrated circuit includes a first ion implantation process implanting impurity ions of a second conductivity type into a bottom surface of a semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a first current suppression layer, and a second ion implantation process implanting impurity ions of a first conductivity type into the bottom surface of the semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a second current suppression layer. The semiconductor integrated circuit includes a first well region of the first conductivity type and a second well region of the second conductivity type provided in an upper portion of the first well region. The first current suppression layer is separated from the first well region and the second current suppression layer is provided under the first current suppression layer.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi KANNO, Masaharu YAMAJI, Hitoshi SUMIDA
  • Patent number: 10825812
    Abstract: A semiconductor integrated circuit includes: a first well region of a first conductivity type; a second well region of a second conductivity type provided in an upper portion of the first well region; a first current suppression layer of a second conductivity type being provided to be separated from the first well region in a lower portion of a base-body of the second conductivity type directly under the first well region and having an impurity concentration higher than that of the base-body; and a second current suppression layer of the first conductivity type provided under the first current suppression layer so as to be exposed from a bottom surface of the base-body.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: November 3, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Kanno, Masaharu Yamaji, Hitoshi Sumida
  • Publication number: 20200328203
    Abstract: A semiconductor integrated circuit includes a high-potential-side circuit region, a high-voltage junction termination structure surrounding the high-potential-side circuit region, and a low-potential-side circuit region surrounding the high-potential-side circuit region via the high-voltage junction termination structure which are integrated into a single chip, and wherein a first distance between a looped well region and a buried layer in a region in which a first contact region is formed is smaller than a second distance between the looped well region and the buried layer in a region in which a carrier reception region is formed.
    Type: Application
    Filed: March 9, 2020
    Publication date: October 15, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu Yamaji
  • Patent number: 10727180
    Abstract: A resistive element includes: a semiconductor substrate; a first insulating film deposited on the semiconductor substrate; a resistive layer deposited on the first insulating film; a second insulating film deposited to cover the first insulating film and the resistive layer; a first electrode deposited on the second insulating film and electrically connected to the resistive layer; a relay wire deposited on the second insulating film without being in contact with the first electrode, and including a resistive-layer connection terminal electrically connected to the resistive layer and a substrate connection terminal connected to the semiconductor substrate with an ohmic contact; and a second electrode deposited on a bottom side of the semiconductor substrate, wherein a resistor is provided between the first electrode and the second electrode.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: July 28, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Taichi Karino, Hitoshi Sumida, Masaru Saito, Masaharu Yamaji, Osamu Sasaki
  • Publication number: 20200161418
    Abstract: A semiconductor integrated circuit includes: a semiconductor base body of a first conductivity type; a first well region of a second conductivity type, deposited at an upper portion of the semiconductor base body, to which a first potential is applied; a second well region of the first conductivity type, deposited at an upper portion of the first well region, to which a second potential lower than the first potential is applied; a main electrode region to which the second potential is applied, the main electrode region being deposited at the upper portion of the first well region and away from the second well region; a first buried layer of the second conductivity type buried locally under the second well region; and a second buried layer of the second conductivity type buried locally under the main electrode region and away from the first buried layer.
    Type: Application
    Filed: September 24, 2019
    Publication date: May 21, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu YAMAJI
  • Patent number: 10658504
    Abstract: A p?-type isolation region is provided at a part between a p-type ground region and a circuit region (a high potential region and an intermediate potential region) in an n-type well region. The p?-type isolation region is electrically connected with a H-VDD pad and an n+-type drain region of a HVNMOS. The p?-type isolation region has between n+-type pickup connect regions and between n+-type drain regions of two of the HVNMOSs, a protruding part (a T-shaped part, an L-shaped part, a partial U-shaped part) or an additional part that protrudes toward a p-ground region.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 19, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu Yamaji
  • Patent number: 10566412
    Abstract: An interlayer insulating film is disposed on a LOCOS oxide film covering an n-type drift region of a JFET. A polysilicon resistor having a spiral planar shape is disposed in the interlayer insulating film. A spiral wire in an outermost circumference of the polysilicon resistor is covered by a source electrode wire that extends on the interlayer insulating film. An end of the polysilicon resistor is electrically connected to a drain electrode wire. A ground terminal wire and a voltage division terminal wire are electrically connected to a spiral wire farther on an inner circumference side by one or more wires than the spiral wire. A portion farther on an inner circumference side than the spiral wire is used as a resistive element, and voltage for an input pad of the JFET is thereby divided to be taken out as a potential of the voltage division terminal wire.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: February 18, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Taichi Karino, Masaharu Yamaji
  • Patent number: 10566410
    Abstract: Warping of a semiconductor wafer occurring due to a difference in the thermal expansion rates of an insulating film and the semiconductor wafer is restricted. Therefore, processing failures and conveying failures in the manufacturing process, as well as cracking of the semiconductor wafer, are restricted. Provided is a high breakdown voltage passive element including a substrate, a lower metal layer and upper metal layer stacked on the substrate, and an insulating unit formed between the lower metal layer and upper metal layer, wherein the insulating unit has a first insulating film whose thermal expansion rate is lower than the thermal expansion rate of the substrate, and a second insulating film, formed on the first insulating film, whose thermal expansion rate is higher than the thermal expansion rate of the substrate.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: February 18, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu Yamaji
  • Publication number: 20200044011
    Abstract: Provided is a resistance element, including: a semiconductor substrate; a first insulating film stacked on the semiconductor substrate; a resistance layer selectively stacked on the first insulating film; a first auxiliary film separated from the resistance layer; a second auxiliary film separated from the resistance layer in a direction different from that of the first auxiliary film; a second insulating film stacked on the first insulating film to cover the resistance layer, and the first auxiliary film and the second auxiliary film; a first electrode connected to the resistance layer and stacked on the second insulating film disposed on an upper side of the first auxiliary film; and a second electrode connected to the resistance layer by being separated from the first electrode and stacked on the second insulating film on the upper side of the second auxiliary film.
    Type: Application
    Filed: June 27, 2019
    Publication date: February 6, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Masaru SAITO, Masaharu YAMAJI, Osamu SASAKI, Hitoshi SUMIDA
  • Publication number: 20200044652
    Abstract: In a level shifter circuit that transmits a set signal and a reset signal input to input terminals of a high-side latch circuit, the source sides of high voltage transistors are connected to current negative feedback resistors, and transistors are connected in parallel to the current negative feedback resistors. Further included is a high-side voltage detection circuit that detects whether the voltage of a high-side power supply terminal is a high voltage. When a high voltage is detected, the transistors are turned OFF to make the drain currents that flow smaller, thereby making it possible to improve the trade-off between heat generation and propagation delay characteristics in the high voltage transistors.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 6, 2020
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Masaharu YAMAJI
  • Patent number: 10547304
    Abstract: A semiconductor integrated circuit for driving a control terminal of a switching device includes: a driver circuit that alternately applies a positive voltage supplied from a positive voltage source and a negative voltage supplied from a negative voltage source to the control terminal in order to switch the switching device ON and OFF; and a negative voltage clamp diode that is integrated into a semiconductor chip on which the driver circuit is formed, an anode thereof being connected to the negative voltage source and a cathode thereof being connected to the control terminal.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: January 28, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaharu Yamaji
  • Patent number: 10396167
    Abstract: A resistive field plate including a spiral resistive element and meander resistive element is provided in an edge termination structure portion. The spiral resistive element is formed in a spiral planar layout, surrounding the periphery of a high-potential-side region to span from the high-potential-side region to a low-potential-side region. A spiral wire of the spiral resistive element includes a conductive film layer and a thin-film resistive layer connected to each other. The meander resistive element has ends positioned in the high-potential-side region and the low-potential-side region, and is provided in a meandering planar layout. The meander resistive element is provided at a same level as that of the thin-film resistive layer, and faces in the depth direction the conductive film layer of the spiral resistive element, sandwiching an interlayer insulating film therebetween. The conductive film layer of the spiral resistive element and the meander resistive element constitute a field plate.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: August 27, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide Tanaka, Masaharu Yamaji
  • Patent number: 10367056
    Abstract: An HVJT is includes a parasitic diode formed by pn junction between an n?-type diffusion region and a second p?-type separation region surrounding a periphery thereof. The n?-type diffusion region is arranged between an n-type diffusion region that is a high potential side region and an n-type diffusion region that is a low potential side region, and electrically separates these regions. In the n?-type diffusion region, an nchMOSFET of a level-up level shift circuit is arranged. The n?-type diffusion region has a planar layout in which the n?-type diffusion region surrounds a periphery of the n-type diffusion region and a region where the nchMOSFET is arranged protrudes inwardly. A high-concentration inter-region distance L1 of the nchMOS region where the nchMOSFET is arranged is longer than a high-concentration inter-region distance L2 of the parasitic diode. Thus, the reliability of the semiconductor device may be improved.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide Tanaka, Masaharu Yamaji