Abstract: In a level shifter circuit that transmits a set signal and a reset signal input to input terminals of a high-side latch circuit, the source sides of high voltage transistors are connected to current negative feedback resistors, and transistors are connected in parallel to the current negative feedback resistors. Further included is a high-side voltage detection circuit that detects whether the voltage of a high-side power supply terminal is a high voltage. When a high voltage is detected, the transistors are turned OFF to make the drain currents that flow smaller, thereby making it possible to improve the trade-off between heat generation and propagation delay characteristics in the high voltage transistors.

Abstract: A semiconductor integrated circuit for driving a control terminal of a switching device includes: a driver circuit that alternately applies a positive voltage supplied from a positive voltage source and a negative voltage supplied from a negative voltage source to the control terminal in order to switch the switching device ON and OFF; and a negative voltage clamp diode that is integrated into a semiconductor chip on which the driver circuit is formed, an anode thereof being connected to the negative voltage source and a cathode thereof being connected to the control terminal.

Abstract: A resistive field plate including a spiral resistive element and meander resistive element is provided in an edge termination structure portion. The spiral resistive element is formed in a spiral planar layout, surrounding the periphery of a high-potential-side region to span from the high-potential-side region to a low-potential-side region. A spiral wire of the spiral resistive element includes a conductive film layer and a thin-film resistive layer connected to each other. The meander resistive element has ends positioned in the high-potential-side region and the low-potential-side region, and is provided in a meandering planar layout. The meander resistive element is provided at a same level as that of the thin-film resistive layer, and faces in the depth direction the conductive film layer of the spiral resistive element, sandwiching an interlayer insulating film therebetween. The conductive film layer of the spiral resistive element and the meander resistive element constitute a field plate.

Abstract: An HVJT is includes a parasitic diode formed by pn junction between an n?-type diffusion region and a second p?-type separation region surrounding a periphery thereof. The n?-type diffusion region is arranged between an n-type diffusion region that is a high potential side region and an n-type diffusion region that is a low potential side region, and electrically separates these regions. In the n?-type diffusion region, an nchMOSFET of a level-up level shift circuit is arranged. The n?-type diffusion region has a planar layout in which the n?-type diffusion region surrounds a periphery of the n-type diffusion region and a region where the nchMOSFET is arranged protrudes inwardly. A high-concentration inter-region distance L1 of the nchMOS region where the nchMOSFET is arranged is longer than a high-concentration inter-region distance L2 of the parasitic diode. Thus, the reliability of the semiconductor device may be improved.

Abstract: A resistive element includes: a semiconductor substrate; a first insulating film deposited on the semiconductor substrate; a resistive layer deposited on the first insulating film; a second insulating film deposited to cover the first insulating film and the resistive layer; a first electrode deposited on the second insulating film and electrically connected to the resistive layer; a relay wire deposited on the second insulating film without being in contact with the first electrode, and including a resistive-layer connection terminal electrically connected to the resistive layer and a substrate connection terminal connected to the semiconductor substrate with an ohmic contact; and a second electrode deposited on a bottom side of the semiconductor substrate, wherein a resistor is provided between the first electrode and the second electrode.

Abstract: Warping of a semiconductor wafer occurring due to a difference in the thermal expansion rates of an insulating film and the semiconductor wafer is restricted. Therefore, processing failures and conveying failures in the manufacturing process, as well as cracking of the semiconductor wafer, are restricted. Provided is a high breakdown voltage passive element including a substrate, a lower metal layer and upper metal layer stacked on the substrate, and an insulating unit formed between the lower metal layer and upper metal layer, wherein the insulating unit has a first insulating film whose thermal expansion rate is lower than the thermal expansion rate of the substrate, and a second insulating film, formed on the first insulating film, whose thermal expansion rate is higher than the thermal expansion rate of the substrate.

Abstract: A p?-type isolation region is provided at a part between a p-type ground region and a circuit region (a high potential region and an intermediate potential region) in an n-type well region. The p?-type isolation region is electrically connected with a H-VDD pad and an n+-type drain region of a HVNMOS. The p?-type isolation region has between n+-type pickup connect regions and between n+-type drain regions of two of the HVNMOSs, a protruding part (a T-shaped part, an L-shaped part, a partial U-shaped part) or an additional part that protrudes toward a p-ground region.

Abstract: A semiconductor integrated circuit for driving a control terminal of a switching device includes: a driver circuit that alternately applies a positive voltage supplied from a positive voltage source and a negative voltage supplied from a negative voltage source to the control terminal in order to switch the switching device ON and OFF; and a negative voltage clamp diode that is integrated into a semiconductor chip on which the driver circuit is formed, an anode thereof being connected to the negative voltage source and a cathode thereof being connected to the control terminal.

Abstract: Warping of a semiconductor wafer occurring due to a difference in the thermal expansion rates of an insulating film and the semiconductor wafer is restricted. Therefore, processing failures and conveying failures in the manufacturing process, as well as cracking of the semiconductor wafer, are restricted. Provided is a high breakdown voltage passive element including a substrate, a lower metal layer and upper metal layer stacked on the substrate, and an insulating unit formed between the lower metal layer and upper metal layer, wherein the insulating unit has a first insulating film whose thermal expansion rate is lower than the thermal expansion rate of the substrate, and a second insulating film, formed on the first insulating film, whose thermal expansion rate is higher than the thermal expansion rate of the substrate.

Abstract: A semiconductor integrated circuit includes a semiconductor layer of a first conductivity type which is stacked on a support substrate with an insulating layer interposed between the semiconductor layer and the support substrate, a first well region of a second conductivity type buried in an upper part of the semiconductor layer so as to be separated from the insulating layer, a second well region of the first conductivity type buried in an upper part of the first well region, and an isolation region of the first conductivity type buried in the upper part of the semiconductor layer such that the isolation region surrounds the first well region and is separated from the first well region and the insulating layer.

Abstract: An nchMOSFET of a level-raising circuit is arranged in a high voltage junction termination region (HVJT), to be integrated with a parasitic diode formed by an n?-type diffusion region and a second p-type separation region. On a high potential side of the HVJT, a first field plate (FP) also acting as a drain electrode of the nchMOSFET and a second FP also acting as a cathode electrode of a parasitic diode are arranged away from each other. On a low potential side the HVJT, a third electrode also acting as a source electrode of the nchMOSFET is arranged in a planar layout surrounding the periphery of a high potential side region. On an interlayer insulating film, an interval between a first portion of the third FP and a fourth portion of the first FP is larger than an interval between the second and the third FPs.

Abstract: An HVNMOS having a source follower configuration is disposed in an n? diffusion region that forms an HVJT. The lateral HVNMOS includes a p-type back gate region, source contact region, n+drain region, and gate electrode. The p-type back gate region and source contact region contact a p? isolation region and are separated from p+ common potential regions inside the p? isolation region. The source contact region is electrically connected to the COM electrode pad through a source follower resistor RSF. The p+ common potential regions are electrically connected to the p-type back gate region and source contact region of the HVNMOS through diffusion resistors provided between the p-type back gate region/source contact region of the HVNMOS and the p+ common potential region.

Abstract: A semiconductor integrated circuit device, including a semiconductor layer of a first conductivity type, a first well region of a second conductivity type, a second well region of the second conductivity type, and a third well region of the first conductivity type. The device further includes an isolation region electrically isolating a predetermined region in the first well region, a first high-concentration region of the second conductivity type, disposed outside the isolation region and inside one of the first well region and the second well region, and a second high-concentration region of the second conductivity type, disposed inside the isolation region and inside one of the first well region and the second well region. The first and second high-concentration regions each have an impurity concentration that is higher than that of the first well region.

Abstract: A semiconductor integrated circuit includes: a first well region of a first conductivity type; a second well region of a second conductivity type provided in an upper portion of the first well region; a first current suppression layer of a second conductivity type being provided to be separated from the first well region in a lower portion of a base-body of the second conductivity type directly under the first well region and having an impurity concentration higher than that of the base-body; and a second current suppression layer of the first conductivity type provided under the first current suppression layer so as to be exposed from a bottom surface of the base-body.

Abstract: A semiconductor integrated circuit includes a semiconductor substrate of a first conductivity type, a first well region of a second conductivity type formed in an upper portion of the semiconductor substrate, a second well region of the first conductivity type formed in an upper portion of the first well region, an insulating layer formed separated from the first well region on a bottom portion of the semiconductor substrate that is directly beneath the first well region, and a rear surface electrode layer formed on a bottom of the insulating layer.

Abstract: A semiconductor device includes a resistive element wherein a diffusion resistance region provided in an upper portion of a semiconductor base and a thin film resistance layer isolated and distanced from the semiconductor base and diffusion resistance region across an insulating film are alternately connected in series and alternately disposed in parallel.

Abstract: An HVNMOS having a source follower configuration is disposed in an n? diffusion region that forms an HVJT. The lateral HVNMOS includes a p-type back gate region, source contact region, n+drain region, and gate electrode. The p-type back gate region and source contact region contact a p? isolation region and are separated from p+ common potential regions inside the p? isolation region. The source contact region is electrically connected to the COM electrode pad through a source follower resistor RSF. The p+ common potential regions are electrically connected to the p-type back gate region and source contact region of the HVNMOS through diffusion resistors provided between the p-type back gate region/source contact region of the HVNMOS and the p+ common potential region.

Abstract: In a semiconductor device including a bootstrap diode and a high voltage electric field transistor on a p-type semiconductor substrate, a cavity is formed in an n?-type buried layer of the semiconductor substrate to use the buried layer beneath the cavity as a drain drift region of the high voltage n-channel MOSFET, whereby a leakage current by holes that flows to the semiconductor substrate side in forward biasing of the bootstrap diode can be suppressed, and charging current for a bootstrap capacitor C1 can be increased, as well as increase in chip area can be suppressed.

Abstract: Warping of a semiconductor wafer occurring due to a difference in the thermal expansion rates of an insulating film and the semiconductor wafer is restricted. Therefore, processing failures and conveying failures in the manufacturing process, as well as cracking of the semiconductor wafer, are restricted. Provided is a high breakdown voltage passive element including a substrate, a lower metal layer and upper metal layer stacked on the substrate, and an insulating unit formed between the lower metal layer and upper metal layer, wherein the insulating unit has a first insulating film whose thermal expansion rate is lower than the thermal expansion rate of the substrate, and a second insulating film, formed on the first insulating film, whose thermal expansion rate is higher than the thermal expansion rate of the substrate.

Abstract: An HVJT is includes a parasitic diode formed by pn junction between an n?-type diffusion region and a second p?-type separation region surrounding a periphery thereof. The n?-type diffusion region is arranged between an n-type diffusion region that is a high potential side region and an n-type diffusion region that is a low potential side region, and electrically separates these regions. In the n?-type diffusion region, an nchMOSFET of a level-up level shift circuit is arranged. The n?-type diffusion region has a planar layout in which the n?-type diffusion region surrounds a periphery of the n-type diffusion region and a region where the nchMOSFET is arranged protrudes inwardly. A high-concentration inter-region distance L1 of the nchMOS region where the nchMOSFET is arranged is longer than a high-concentration inter-region distance L2 of the parasitic diode. Thus, the reliability of the semiconductor device may be improved.