Patents by Inventor Masaharu Yamaji
Masaharu Yamaji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8674729Abstract: A high voltage semiconductor device is provided and includes an n?-type region encompassed by a p? well region and is provided on a p?-type silicon substrate. A drain n+-region is connected to a drain electrode. A p base region is formed so as to be separate from and encompass the drain n+-region. A source n+-region is formed in the p base region. Further, a p?-region is provided that passes through the n?-type region to the silicon substrate. The n?-type region is divided, by the p?-region, into a drift n?-type region having the drain n+-region and a floating n?-type region having a floating electric potential.Type: GrantFiled: September 29, 2010Date of Patent: March 18, 2014Assignee: Fuji Electric Co., Ltd.Inventor: Masaharu Yamaji
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Patent number: 8633563Abstract: A high-voltage integrated circuit device can include, in a surface layer of a p semiconductor substrate, an n region which is a high-side floating-potential region, an n? region which becomes a high-voltage junction terminating region, and an n? region which is an L-VDD potential region. A low-side circuit portion can be disposed in an n? region. Below a pickup electrode disposed in the high-voltage junction terminating region, a universal contact region in Ohmic contact with the pickup electrode can be disposed. The universal contact region has a p+ region and an n+ region that can be disposed in alternating contact along a surface of the p semiconductor substrate. By disposing the universal contact region in this way, the quantity of carriers flowing into the low-side circuit portion can be reduced when a negative surge voltage is input. Consequently, erroneous operation due to latchup of a logic portion can be minimized.Type: GrantFiled: January 10, 2013Date of Patent: January 21, 2014Assignee: Fuji Electric Co., Ltd.Inventor: Masaharu Yamaji
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Patent number: 8546889Abstract: A high breakdown voltage semiconductor device includes: an n? type region (101) surrounded by a p? well region (102) on a p? type silicon substrate (100); a drain n+ region (103) connected to a drain electrode (120); a p base region (105) formed so as to surround the drain n+ region (103); a source n+ region (114) formed in the p base region (105); and a p? region (131) for isolating the n? type region (101) into an n? type region (101a) including the drain n+ region (103), and an n? type region (101b) not having the drain n+ region (103). The n? type region (101b) is connected to the drain electrode (120) or the drain n+ region (103) via an n offset region (104) or a polysilicon (304) which is a high resistance element.Type: GrantFiled: May 24, 2011Date of Patent: October 1, 2013Assignee: Fuji Electric Co., Ltd.Inventor: Masaharu Yamaji
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Patent number: 8507998Abstract: A semiconductor device can output a reference voltage for an arbitrary potential and can detect the voltage of each cell in a battery including multiple cells very precisely. The device includes a depletion-type MOSFET 21 and an enhancement type MOSFET 22, and has a floating structure that isolates depletion-type MOSFET 21 and enhancement type MOSFET 22 from a ground terminal. The depletion-type MOSFET 21 and enhancement type MOSFET 22 are connected in series to each other, wherein the depletion-type MOSFET 21 is connected to high-potential-side terminal and the enhancement type MOSFET 22 is connected to low-potential-side terminal. The semiconductor device having the configuration described above is disposed in a voltage detecting circuit section in a control IC for a battery including multiple cells.Type: GrantFiled: February 29, 2012Date of Patent: August 13, 2013Assignee: Fuji Electric Co., Ltd.Inventors: Masaharu Yamaji, Akio Kitamura
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Patent number: 8368141Abstract: A high breakdown voltage semiconductor device, in which a semiconductor layer is formed on a semiconductor substrate across a dielectric layer, includes a drain layer on the semiconductor layer, a buffer layer formed so as to envelop the drain layer, a source layer, separated from the drain layer, and formed so as to surround a periphery thereof, a well layer formed so as to envelop the source layer, and a gate electrode formed across a gate insulating film on the semiconductor layer, wherein the planar shape of the drain layer 113 and buffer layer is a non-continuous or continuous ring.Type: GrantFiled: March 8, 2010Date of Patent: February 5, 2013Assignee: Fuji Electric Co., Ltd.Inventor: Masaharu Yamaji
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Publication number: 20130001736Abstract: A high-voltage integrated circuit device has formed therein a high-voltage junction terminating region that is configured by a breakdown voltage region formed of an n-well region, a ground potential region formed of a p-region, a first contact region and a second contact region. An opposition section of the high-voltage junction terminating region, whose distance to an intermediate-potential region formed of a p-drain region is shorter than those of other sections, is provided with a resistance higher than those of the other sections. Accordingly, a cathode resistance of a parasitic diode formed of the p-region and the n-well region increases, locally reducing the amount of electron holes injected at the time of the input of a negative-voltage surge. As a result, an erroneous operation or destruction of a logic part of a high-side circuit can be prevented when the negative-voltage surge is applied to an H-VDD terminal or a Vs terminal.Type: ApplicationFiled: September 12, 2011Publication date: January 3, 2013Applicant: FUJI ELECTRIC CO., LTD.Inventor: Masaharu Yamaji
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Publication number: 20120267750Abstract: A semiconductor apparatus having a bootstrap-type driver circuit includes a cavity for a SON structure formed below a bootstrap diode Db, and a p-type floating region formed in a n? epitaxial layer between a bootstrap diode Db and a p-type GND region at the ground potential (GND). The p-type floating region extends to the cavity for suppressing the leakage current caused by the holes flowing to the p? substrate in charging an externally attached bootstrap capacitor C1. The semiconductor apparatus which includes a bootstrap-type driver circuit facilitates suppressing the leakage current caused by the holes flowing to the p? substrate, when the bootstrap diode is biased in forward.Type: ApplicationFiled: April 17, 2012Publication date: October 25, 2012Applicant: FUJI ELECTRONIC CO., LTD.Inventors: Tomohiro IMAI, Masaharu Yamaji
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Publication number: 20120235712Abstract: A high voltage semiconductor device is provided and includes an n?-type region encompassed by a p? well region and is provided on a p?-type silicon substrate. A drain n+-region is connected to a drain electrode. A p base region is formed so as to be separate from and encompass the drain n+-region. A source n+-region is formed in the p base region. Further, a p?-region is provided that passes through the n?-type region to the silicon substrate. The n?-type region is divided, by the p?-region, into a drift n?-type region having the drain n+-region and a floating n?-type region having a floating electric potential.Type: ApplicationFiled: September 29, 2010Publication date: September 20, 2012Applicant: Fuji Electri Co., Ltd.Inventor: Masaharu Yamaji
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Patent number: 8269305Abstract: Aspects of the present invention provide a high-voltage semiconductor device and a high voltage integrated circuit device while minimizing or eliminating the need for the addition of back surface steps. Aspects of the invention provide a high-voltage semiconductor device that achieves, low voltage driving and quick response by way of stable high voltage wiring and a low ON voltage. In some aspects of the invention, a high-voltage semiconductor device can include a semiconductor layer is formed on a support substrate interposing an embedded oxide film therebetween. A high potential side second stage transistor and a low potential side first stage transistor surrounding the second stage transistor are formed on the surface region of the semiconductor layer. The source electrode of the second stage transistor is connected to the drain electrode of the first stage transistor. A drain electrode of the second stage transistor is connected to a drain pad.Type: GrantFiled: June 10, 2010Date of Patent: September 18, 2012Assignee: Fuji Electric Co., Ltd.Inventor: Masaharu Yamaji
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Patent number: 8242572Abstract: A semiconductor apparatus includes, below a high-voltage wiring, a p? diffusion layer in contact with an n drain buffer layer and a p+ diffusion layer in contact with a p? diffusion layer for reducing the electric field strength in an insulator film, which the high-voltage wiring crosses over. Reducing electric field strength in the insulator film prevents lowering of breakdown voltage of a high-voltage NMOSFET, break down of an interlayer insulator film, and impairment of isolation breakdown voltage of a device isolation trench. The semiconductor apparatus according to the invention facilitates bridging a high-voltage wiring from a high-voltage NMOSFET and such a level-shifting device to a high-voltage floating region crossing over a device isolation trench without impairing the breakdown voltage of the high-voltage NMOSFET, without breaking down the interlayer insulator film and without impairing the isolation breakdown voltage of the device isolation trench.Type: GrantFiled: November 2, 2010Date of Patent: August 14, 2012Assignee: Fuji Electric Co., Ltd.Inventor: Masaharu Yamaji
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Publication number: 20120161246Abstract: A semiconductor device can output a reference voltage for an arbitrary potential and can detect the voltage of each cell in a battery including multiple cells very precisely. The device includes a depletion-type MOSFET 21 and an enhancement type MOSFET 22, and has a floating structure that isolates depletion-type MOSFET 21 and enhancement type MOSFET 22 from a ground terminal. The depletion-type MOSFET 21 and enhancement type MOSFET 22 are connected in series to each other, wherein the depletion-type MOSFET 21 is connected to high-potential-side terminal and the enhancement type MOSFET 22 is connected to low-potential-side terminal. The semiconductor device having the configuration described above is disposed in a voltage detecting circuit section in a control IC for a battery including multiple cells.Type: ApplicationFiled: February 29, 2012Publication date: June 28, 2012Applicant: FUJI ELECTRIC CO., LTD.Inventors: Masaharu YAMAJI, Akio KITAMURA
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Patent number: 8148785Abstract: A semiconductor device can output a reference voltage for an arbitrary potential and can detect the voltage of each cell in a battery including multiple cells very precisely. The device includes a depletion-type MOSFET 21 and an enhancement type MOSFET 22, and has a floating structure that isolates depletion-type MOSFET 21 and enhancement type MOSFET 22 from a ground terminal. The depletion-type MOSFET 21 and enhancement type MOSFET 22 are connected in series to each other, wherein the depletion-type MOSFET 21 is connected to high-potential-side terminal and the enhancement type MOSFET 22 is connected to low-potential-side terminal. The semiconductor device having the configuration described above is disposed in a voltage detecting circuit section in a control IC for a battery including multiple cells.Type: GrantFiled: September 15, 2008Date of Patent: April 3, 2012Assignee: Fuji Electric Co., Ltd.Inventors: Masaharu Yamaji, Akio Kitamura
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Publication number: 20110133269Abstract: A semiconductor apparatus includes, below a high-voltage wiring, a p? diffusion layer in contact with an n drain buffer layer and a p+ diffusion layer in contact with a p? diffusion layer for reducing the electric field strength in an insulator film, which the high-voltage wiring crosses over. Reducing electric field strength in the insulator film prevents lowering of breakdown voltage of a high-voltage NMOSFET, break down of an interlayer insulator film, and impairment of isolation breakdown voltage of a device isolation trench. The semiconductor apparatus according to the invention facilitates bridging a high-voltage wiring from a high-voltage NMOSFET and such a level-shifting device to a high-voltage floating region crossing over a device isolation trench without impairing the breakdown voltage of the high-voltage NMOSFET, without breaking down the interlayer insulator film and without impairing the isolation breakdown voltage of the device isolation trench.Type: ApplicationFiled: November 2, 2010Publication date: June 9, 2011Applicant: FUJI ELECTRIC SYSTEMS CO., LTD.Inventor: Masaharu YAMAJI
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Publication number: 20100314710Abstract: Aspects of the present invention provide a high-voltage semiconductor device and a high voltage integrated circuit device while minimizing or eliminating the need for the addition of back surface steps. Aspects of the invention provide a high-voltage semiconductor device that achieves, low voltage driving and quick response by way of stable high voltage wiring and a low ON voltage. In some aspects of the invention, a high-voltage semiconductor device can include a semiconductor layer is formed on a support substrate interposing an embedded oxide film therebetween. A high potential side second stage transistor and a low potential side first stage transistor surrounding the second stage transistor are formed on the surface region of the semiconductor layer. The source electrode of the second stage transistor is connected to the drain electrode of the first stage transistor. A drain electrode of the second stage transistor is connected to a drain pad.Type: ApplicationFiled: June 10, 2010Publication date: December 16, 2010Applicant: FUJI ELECTRIC SYSTEMS CO. LTD.Inventor: Masaharu YAMAJI
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Publication number: 20100264491Abstract: A high breakdown voltage semiconductor device, in which a semiconductor layer is formed on a semiconductor substrate across a dielectric layer, includes a drain layer on the semiconductor layer, a buffer layer formed so as to envelop the drain layer, a source layer, separated from the drain layer, and formed so as to surround a periphery thereof, a well layer formed so as to envelop the source layer, and a gate electrode formed across a gate insulating film on the semiconductor layer, wherein the planar shape of the drain layer 113 and buffer layer is a non-continuous or continuous ring.Type: ApplicationFiled: March 8, 2010Publication date: October 21, 2010Applicant: FUJI ELECTRIC SYSTEMS CO. LTD.Inventor: Masaharu YAMAJI
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Publication number: 20090072867Abstract: A semiconductor device can output a reference voltage for an arbitrary potential and can detect the voltage of each cell in a battery including multiple cells very precisely. The device includes a depletion-type MOSFET 21 and an enhancement type MOSFET 22, and has a floating structure that isolates depletion-type MOSFET 21 and enhancement type MOSFET 22 from a ground terminal. The depletion-type MOSFET 21 and enhancement type MOSFET 22 are connected in series to each other, wherein the depletion-type MOSFET 21 is connected to high-potential-side terminal and the enhancement type MOSFET 22 is connected to low-potential-side terminal. The semiconductor device having the configuration described above is disposed in a voltage detecting circuit section in a control IC for a battery including multiple cells.Type: ApplicationFiled: September 15, 2008Publication date: March 19, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Masaharu YAMAJI, Akio KITAMURA
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Publication number: 20080135927Abstract: An insulated gate semiconductor device, specifically, a trench lateral MOSFET having improved hot carrier resistance can be provided without increasing the number of processes and device pitch and without degrading device breakdown voltages and on-resistance characteristics RonA. A junction depth Xj of a p base region of a TLPM (trench lateral power MOSFET) is made smaller than the depth of a trench, and the trench is formed with a depth Dt of about 1.2 ?m such that the junction does not contact a curved corner part at the bottom of the trench.Type: ApplicationFiled: November 21, 2007Publication date: June 12, 2008Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventors: Masaharu YAMAJI, Naoto FUJISHIMA, Mutsumi KITAMURA
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Patent number: 7144781Abstract: A plurality of trenches, about 1 ?m long in the Z-direction that crosses the X-direction (source-drain direction), are formed in a semiconductor substrate, arranged in the Z-direction. Ion implantation is performed obliquely with respect to side faces of each trench that cross the X-direction. Then, ion implantation is performed perpendicularly to the bottom face of each trench. Then, oxidation and drive-in are performed, whereby semiconductor portions between adjacent trenches are oxidized and each trench is thereby filled with an oxide to establish a wide trench region as would be obtained by connecting the trenches. At the same time, the impurity ions implanted around the trenches are diffused also in the Z-direction, whereby a uniform offset drain region is formed around the trench so that an optimum concentration and diffusion of the impurity ions is obtained, and an oxide or the like is buried in a wide trench region.Type: GrantFiled: June 15, 2004Date of Patent: December 5, 2006Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Masaharu Yamaji, Akio Kitamura, Naoto Fujishima
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Publication number: 20050020040Abstract: A plurality of trenches, about 1 ?m long in the Z-direction that crosses the X-direction (source-drain direction), are formed in a semiconductor substrate, arranged in the Z-direction. Ion implantation is performed obliquely with respect to side faces of each trench that cross the X-direction. Then, ion implantation is performed perpendicularly to the bottom face of each trench. Then, oxidation and drive-in are performed, whereby semiconductor portions between adjacent trenches are oxidized and each trench is thereby filled with an oxide to establish a wide trench region as would be obtained by connecting the trenches. At the same time, the impurity ions implanted around the trenches are diffused also in the Z-direction, whereby a uniform offset drain region is formed around the trench so that an optimum concentration and diffusion of the impurity ions is obtained, and an oxide or the like is buried in a wide trench region.Type: ApplicationFiled: June 15, 2004Publication date: January 27, 2005Inventors: Masaharu Yamaji, Akio Kitamura, Naoto Fujishima