Patents by Inventor Masahiro Sunohara

Masahiro Sunohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120261801
    Abstract: A wiring board includes a silicon substrate with a through hole communicating with first and second substrate surfaces. A capacitor includes a capacitor part mounted on an insulating film covering the substrate first surface and including a first electrode on the insulating film, a first dielectric layer on the first electrode, and a second electrode on the first dielectric layer. A multilayer structure arranged on a wall surface defining the through hole includes the insulating film on the through hole wall surface, a first metal layer on the insulating film formed from the same material as the first electrode, a second dielectric layer on the first metal layer formed from the same material as the first dielectric layer, and a second metal layer on the second dielectric layer formed from the same material as the second electrode. The multilayer structure covers a penetration electrode in the through hole.
    Type: Application
    Filed: April 17, 2012
    Publication date: October 18, 2012
    Applicants: TAIYO YUDEN CO., LTD., SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Akihito TAKANO, Masahiro SUNOHARA, Hideaki SAKAGUCHI, Mitsutoshi HIGASHI, Kenichi OTA, Yuichi SASAJIMA
  • Publication number: 20120261832
    Abstract: A wiring board provided with a silicon substrate including a through hole that communicates a first surface and a second surface of the silicon substrate. A capacitor is formed on an insulating film, which is applied to the silicon substrate, on the first surface and a wall surface defining the through hole. A capacitor part of the capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially deposited on the insulating film on the first surface and the wall surface of the through hole. A penetration electrode is formed in the through hole covered by the first electrode, the dielectric layer, and the second electrode of the capacitor part.
    Type: Application
    Filed: April 17, 2012
    Publication date: October 18, 2012
    Applicants: TAIYO YUDEN CO., LTD., SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Akihito TAKANO, Masahiro SUNOHARA, Hideaki SAKAGUCHI, Mitsutoshi HIGASHI, Kenichi OTA, Yuichi SASAJIMA
  • Patent number: 8212365
    Abstract: A printed wiring board is configured to be connected to an organic substrate in a state where a semiconductor chip is mounted thereon. A plurality of first layers are formed of a material having the same coefficient of thermal expansion as the semiconductor chip. A plurality of second layers are formed of a material having the same coefficient of thermal expansion as the organic substrate. The first layers have different thicknesses from each other and the second layers have different thicknesses from each other. The first layers and the second layers form a lamination by being laminated alternately one on another. The thicknesses of the first layers decrease from a side where the semiconductor chip is mounted toward a side where the organic substrate is connected. The thicknesses of the second layers decrease from the side where the organic substrate is connected toward the side where the semiconductor chip is mounted.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: July 3, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Keisuke Ueda
  • Patent number: 8212355
    Abstract: A semiconductor package includes a semiconductor device, and a wiring board where the semiconductor device is mounted. The semiconductor device includes a semiconductor substrate, a piercing electrode configured to pierce the semiconductor substrate and electrically connect the wiring board and the semiconductor device, and a ring-shaped concave part provided so as to surround the piercing electrode, the ring-shaped concave part being configured to open to a wiring board side of the semiconductor substrate.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: July 3, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Yuichi Taguchi
  • Patent number: 8183469
    Abstract: A wiring board includes an external connection terminal of a cylindrical shape, in which an electrode terminal of the electronic component to be mounted is fitted. In one configuration, a portion of the external connection terminal is electrically connected to a pad portion formed on an electronic component mounting surface side of the wiring board, and the external connection terminal is curvedly formed in such a shape that the outer periphery of the electrode terminal comes into close contact with the inner periphery of the middle portion of the external connection terminal when the electrode terminal is inserted into the external connection terminal.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: May 22, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kei Murayama, Takaharu Yamano
  • Patent number: 8183679
    Abstract: A peeling off layer 18 is formed on an entire surface of one surface side of a support plate 10 including the inner wall surfaces respectively of a recessed part 12 for an electronic part and recessed parts 16 for posts in which the posts 20 are formed. Then, the recessed parts 16 are filled with metal to form the posts 20. Then, conductor patterns 28 are formed that electrically connect the electrode terminals 22a of the electronic part 22 inserted into the recessed part 12 to the posts 20. Then, an insulating layer covering the conductor patterns 28 is formed to form an electronic part package 30 on the one surface side of the support plate 10 through the peeling off layer 18. After that, the electronic part package 30 is separated from the support plate 10 by the peeling off layer 18.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: May 22, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Hideaki Sakaguchi, Masahiro Sunohara, Mitsutoshi Higashi
  • Patent number: 8148738
    Abstract: In a semiconductor device 100, a light emitting element 120 has been mounted on an upper plane of a semiconductor substrate 102. In an impurity diffusion region of the semiconductor substrate 102, a P conducting type of a layer 104, and an N layer 106 have been formed, while an N conducting type impurity is implanted to the P layer 104, and then the implanted impurity is diffused to constitute the N layer 106. A zener diode 108 made of a semiconductor device has been formed by the P layer 104 and the N layer 106.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: April 3, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kei Murayama, Mitsutoshi Higashi, Naoyuki Koizumi, Yuichi Taguchi, Akinori Shiraishi, Masahiro Sunohara
  • Patent number: 8137497
    Abstract: A method includes the steps of providing a first tape base material on a single side of a stiffener substrate, forming, on the stiffener substrate, a cavity for accommodating a semiconductor chip therein, inserting the stiffener substrate in the cavity and providing the stiffener substrate on the first tape base material, sealing the semiconductor chip and the stiffener substrate with a sealing resin, and removing the first tape base material and forming a build-up layer on a tape removing surface.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: March 20, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kei Murayama, Mitsutoshi Higashi, Hideaki Sakaguchi
  • Patent number: 8119932
    Abstract: First, a structure is fabricated by directly bonding a first base material and a second base material. The first base material has a recessed portion formed in a desired patterning layout on one surface thereof, and the bonding is performed in such a manner that the surface having the recessed portion of the first base material faces inward. Then, through holes are formed at desired positions in the structure in such a manner that the through holes pierce the structure in a direction of thickness thereof and communicate with the corresponding recessed portions. Further, an insulating layer is formed on the surface of the structure, and thereafter, a conductive material is filled into the through holes and the recessed portions.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: February 21, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Masahiro Sunohara
  • Patent number: 8111523
    Abstract: A wiring board for use in mounting an electronic component includes a switch element portion interposed in a signal transmission line including a wiring layer linked to an electrode terminal of the electronic component. The switch element portion has such a structure as to change the shape thereof depending on a temperature, and to disconnect the signal transmission line when the temperature exceeds a predetermined temperature. A conductor layer which constitutes a portion of the signal transmission line is formed at the bottom of a cavity formed in an electronic component mounting surface side of the wiring board. One end of the switch element portion is fixedly connected to the wiring layer, and another end thereof is in contact with the conductor layer when the temperature is equal to or lower than the predetermined temperature.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: February 7, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kei Murayama
  • Patent number: 8108993
    Abstract: A method of manufacturing a wiring substrate is disclosed. The method includes: (a) preparing a supporting substrate including a main body and a through electrode penetrating the main body, wherein the supporting substrate includes a first surface and a second surface opposite to the first surface, and a trace is formed on the second surface of the supporting substrate; (b) forming a build-up wiring structure by alternately forming a wiring layer and an insulating layer on the first surface of the supporting substrate; and (c) obtaining a wiring substrate by separating the build-up wiring structure from the supporting substrate. Step (b) includes: forming the wiring layer using the through electrode as a power feeding wiring, and step (c) includes: peeling the build-up wiring structure from the supporting substrate to obtain the wiring substrate.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: February 7, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Mitsutoshi Higashi, Kei Murayama, Masahiro Sunohara, Hideaki Sakaguchi
  • Patent number: 8106484
    Abstract: In a silicon substrate for a package, a through electrode is provided with which a through hole passing through from a bottom surface of a cavity for accommodating a chip of an electronic device to a back surface of the substrate is filled. An end part of the through electrode in the bottom surface side of the cavity has a connection part to a wiring that forms an electric circuit including the chip of the electronic device. The silicon substrate for a package is characterized in that (1) a thin film wiring is included as the wiring and the connection part is reinforced by a conductor connected to the thin film wiring and/or (2) a wire bonding part is included as the wiring and the connection part is formed by wire bonding the end part of the through electrode in the bottom surface side of the cavity.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: January 31, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Akinori Shiraishi, Kei Murayama, Yuichi Taguchi, Masahiro Sunohara, Mitsutoshi Higashi
  • Patent number: 8100555
    Abstract: It is a lighting apparatus 10 that has a light emitting element 16, a light emitting element housing 15 having a concave portion 28 that accommodates the light emitting element 16, and an optically transparent member 18 that airproofs a space B formed by the concave portion 28 and transmits light emitted from the light emitting element 16. The concave portion 28 is shaped to become wider toward the optically transparent member 18 from the bottom surface 28A of the concave portion 28. The lighting apparatus 10 is provided with a light shielding member 12 for shielding a part of light emitted from the light emitting element 16 is provided on the optically transparent member 18.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: January 24, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Mitsutoshi Higashii, Kei Murayama, Yuichi Taguchi, Masahiro Sunohara, Akinori Shiraishi
  • Publication number: 20110316169
    Abstract: A wiring substrate includes a substrate body including a first substrate surface and a second substrate surface, a trench being open toward the first substrate surface, the trench having an inner bottom surface and an inner side surface, a through-hole having a first end communicating with the inner bottom surface of the trench and a second end being open toward the second substrate surface, a first conductive layer having a first surface toward the trench and being filled inside at least a portion of the through-hole from the second end, a second conductive layer covering the first surface and at least a part of the inner bottom surface of the trench, and a third conductive layer covering the second conductive layer and being filled inside the trench.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 29, 2011
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Masahiro SUNOHARA, Takayuki TOKUNAGA, Hedeaki SAKAGUCHI, Akihito TAKANO
  • Patent number: 8080122
    Abstract: There are provided a step of preparing a dummy chip, a step of forming a cavity in a stiffener substrate, a step of providing a second tape base member on one surface of the stiffener substrate, a step of inserting the dummy chip into the cavity to provide the dummy chip on the second tape base member, a step of sealing the stiffener substrate and the dummy chip with a sealing resin, a step of removing the second tape base member and forming a build-up wiring layer on a surface from which the second tape base member is removed, a step of removing the sealing resin; and a step of peeling the dummy chip from the build-up wiring layer.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: December 20, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kei Murayama, Mitsutoshi Higashi, Hideaki Sakaguchi
  • Publication number: 20110297430
    Abstract: A wiring substrate includes a wiring layer made of copper, an electrode layer made of copper, and an insulating layer arranged adjacent to the electrode layer. The wiring layer is stacked on the electrode layer and the insulating layer. The insulating layer and the wiring layer are stacked with an adhesive layer interposed between the wiring insulating layer and the wiring layer. The electrode layer and the wiring layer are stacked without the adhesive layer interposed between the electrode layer and the wiring layer.
    Type: Application
    Filed: June 6, 2011
    Publication date: December 8, 2011
    Applicant: SHINKO ELECTRIC INDUSTRIESCO., LTD.
    Inventor: Masahiro SUNOHARA
  • Publication number: 20110297426
    Abstract: A wiring substrate includes a wiring layer made of copper, an electrode layer made of copper, and an insulating layer arranged adjacent to the electrode layer. The wiring layer is stacked on the electrode layer and the insulating layer. The insulating layer and the wiring layer are stacked with an adhesive layer interposed between the insulating layer and the wiring layer. The electrode layer and the wiring layer are stacked with a copper alloy layer formed adjacent to the adhesive layer and interposed between the electrode layer and the wiring layer.
    Type: Application
    Filed: June 6, 2011
    Publication date: December 8, 2011
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Masahiro SUNOHARA, Shigeaki SUGANUMA
  • Patent number: 8062927
    Abstract: A wiring board is provided with an external connection terminal to which an electrode terminal of an electronic component is to be connected. The external connection terminal is formed so that a portion thereof is electrically connected to a pad portion exposed from an outermost insulating layer on an electronic component mounting surface of a wiring board body and so that an air gap is kept between a portion of the external connection terminal, to which the electrode terminal of the electronic component is to be connected, and the insulating layer.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: November 22, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Sunohara, Kiyoshi Ol
  • Patent number: 8053886
    Abstract: A semiconductor package includes a wiring board and a semiconductor device mounted on the wiring board. At least one penetration hole extends from one surface of the semiconductor chip to an opposite surface of the semiconductor chip. A penetration electrode is situated inside the penetration hole without contacting a wall of the penetration hole. The penetration electrode has one end fixed to the one surface of the semiconductor chip and an opposite end protruding from the opposite surface of the semiconductor chip. A connection terminal is formed on the opposite end of the penetration electrode and electrically connected to the wiring board.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: November 8, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yuichi Taguchi, Mitsutoshi Higashi, Akinori Shiraishi, Hideaki Sakaguchi, Masahiro Sunohara
  • Publication number: 20110266697
    Abstract: A peeling off layer 18 is formed on an entire surface of one surface side of a support plate 10 including the inner wall surfaces respectively of a recessed part 12 for an electronic part and recessed parts 16 for posts in which the posts 20 are formed. Then, the recessed parts 16 are filled with metal to form the posts 20. Then, conductor patterns 28 are formed that electrically connect the electrode terminals 22a of the electronic part 22 inserted into the recessed part 12 to the posts 20. Then, an insulating layer covering the conductor patterns 28 is formed to form an electronic part package 30 on the one surface side of the support plate 10 through the peeling off layer 18. After that, the electronic part package 30 is separated from the support plate 10 by the peeling off layer 18.
    Type: Application
    Filed: July 14, 2011
    Publication date: November 3, 2011
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Hideaki SAKAGUCHI, Masahiro Sunohara, Mitsutoshi Higashi