Abstract: A semiconductor package includes: a wiring board; and a semiconductor device which is formed on the wiring board; wherein the semiconductor device includes: a semiconductor chip; and a penetration electrode, one end of which is fixed on one plane of the semiconductor chip, and the other end of which penetrates the semiconductor chip and is fixed on the other plane of the semiconductor chip, the penetration electrode penetrating the semiconductor chip in such a manner that the penetration electrode is not contacted to a wall plane of the semiconductor chip by a space portion formed in the semiconductor chip; and the wiring board and the semiconductor device are electrically connected via the penetration electrode.

Abstract: A package for electronic component comprises a rectangular package body having a flat cut surface to be abutted on a flat mounting surface of a mounting substrate, a first side surface intersecting with the flat cut surface, and a first notch part formed at a boundary between the flat cut surface and the first side surface, an electronic component installed in the package body, and a first pad electrically connected to the electronic component and formed on an inner wall surface of the first notch part.

Abstract: A method for fabricating an electronic component embedded substrate including an electronic component that is embedded within a buildup layer is disclosed. The method includes a first buildup layer lamination step of laminating plural first buildup layers on a core substrate such that the total thickness of the first buildup layers corresponds to the thickness of the electronic component; a cavity formation step of forming a cavity for accommodating the electronic component at the laminated first buildup layers; an accommodating step of accommodating the electronic component within the cavity; and a second buildup layer lamination step of laminating a second buildup layer on the first buildup layers and the electronic component.

Abstract: A conveyance system for a semiconductor wafer can be used without any change before and after a support plate is adhered to the wafer. Also, the finish accuracy of the wafer and the positioning accuracy between the wafer and the support plate can be relaxed, thus improving the manufacturing efficiency. The wafer is formed on its peripheral portion with a stepped portion, which is deeper than a finished thickness obtained by partial removal of the rear surface thereof and which can be eliminated by the partial removal of the wafer rear surface. The separation portion has a length which extends radially outward from a flat surface, and which is greater than a total sum of a maximum-minimum difference between the finish allowances of the diameters of the wafer and the support plate, and a maximum value of a positioning error between the wafer and the support plate generated upon adhesion thereof.

Abstract: A method of producing a light emitting apparatus including a light emitting element, a light emitting element housing having a recess for housing the light emitting element, and a translucent substrate placed on the light emitting element housing is disclosed. The disclosed method includes a fluorescent-substance-containing resin forming step of forming a fluorescent-substance-containing resin on a first side of the translucent substrate which first side is opposite to a second side of the translucent substrate which second side faces the recess. In the fluorescent-substance-containing resin forming step, luminance and chromaticity of light that is emitted from the light emitting element and then transmitted by the fluorescent-substance-containing resin are measured and a thickness of the fluorescent-substance-containing resin is adjusted based on the measured luminance and chromaticity so that light emitted from the light emitting apparatus attains the specified luminance and chromaticity.

Abstract: A method of manufacturing an electronic component built-in substrate, includes the steps of mounting a chip-like electronic component having a connection pad and a metal protection layer formed on a whole of one surface to cover the connection pad, on a wiring substrate to direct the connection pad upward; embedding the electronic component with the insulating layer; processing the insulating layer in a thickness direction to leave the insulating layer in a side of the electronic component and to expose the metal protection layer of the electronic component; and forming an upper wiring layer having an in-chip wiring part which is connected to the connection pad and contacts an upper surface of the electronic component and is constructed by an underlying metal pattern layer formed by patterning the metal protection layer and a conductive pattern layer formed thereon, and an extended wiring part which is connected to the in-chip wiring part to extend onto the insulating layer and is formed by an identical layer

Abstract: A semiconductor device includes a laminated substrate formed by laminating a plurality of semiconductor substrates, a concave part formed in the laminated substrate, and a semiconductor element mounted in the concave part. A method of manufacturing a semiconductor device includes a first step of forming a laminated substrate by laminating a plurality of semiconductor substrates, a second step of forming a concave part by etching the laminated substrate, and a third step of mounting a semiconductor element in the concave part.

Abstract: An electronic parts packaging structure of the present invention includes a wiring substrate having a wiring pattern, a first insulating film which is formed on the wiring substrate and which has an opening portion in a packaging area where an electronic parts is mounted, the electronic parts having a connection terminal flip-chip mounted on the wiring pattern exposed in the opening portion of the first insulating film, a second insulating film for covering the electronic parts, a via hole formed in a predetermined portion of the first and second insulating films on the wiring pattern, and an upper wiring pattern formed on the second insulating film and connected to the wiring pattern through the via hole.

Abstract: An interposer includes a substrate made of an inorganic material; a through wiring including conductors embedded in through holes; and an upper wiring and (or) a lower wiring. The through wiring, the upper wiring and the lower wiring are respectively formed on preliminary wiring patterns that are additionally simultaneously or sequentially formed on layers made of an insulating material applied to at least wiring forming parts of the substrate, and are formed with a metal mold itself used for forming the preliminary wiring patterns or layers made of a wiring material applied by a printing operation, a plating operation or a deposition on the preliminary wiring patterns formed on the layers of the insulating material by transferring a fine structure pattern of the metal mold.

Abstract: A peeling off layer 18 is formed on an entire surface of one surface side of a support plate 10 including the inner wall surfaces respectively of a recessed part 12 for an electronic part and recessed parts 16 for posts in which the posts 20 are formed. Then, the recessed parts 16 are filled with metal to form the posts 20. Then, conductor patterns 28 are formed that electrically connect the electrode terminals 22a of the electronic part 22 inserted into the recessed part 12 to the posts 20. Then, an insulating layer covering the conductor patterns 28 is formed to form an electronic part package 30 on the one surface side of the support plate 10 through the peeling off layer 18. After that, the electronic part package 30 is separated from the support plate 10 by the peeling off layer 18.

Abstract: A probe device includes a stage for fixing a semiconductor device having an external connection pad; a heating unit provided in the stage, for heating the semiconductor device to a predetermined temperature; and a probe card having a probe pin and a support substrate for supporting the probe pin, in which a resistance heating element is provided to the support substrate so as to heat a portion of the support substrate corresponding to a disposition portion of the probe pin to a temperature substantially equal to the predetermined temperature.

Abstract: A semiconductor package includes a wiring board and a semiconductor device mounted on the wiring board. At least one penetration hole extends from one surface of the semiconductor chip to an opposite surface of the semiconductor chip. A penetration electrode is situated inside the penetration hole without contacting a wall of the penetration hole. The penetration electrode has one end fixed to the one surface of the semiconductor chip and an opposite end protruding from the opposite surface of the semiconductor chip. A connection terminal is formed on the opposite end of the penetration electrode and electrically connected to the wiring board.

Abstract: There is provided a semiconductor device mounted with a light emitting element, which can be downsized easily, improve light emitting efficiency and be formed easily, and a method for manufacturing the semiconductor device effectively. The semiconductor device includes a substrate, a light emitting element mounted on the substrate by flip chip bonding, a sealing structure sealing the light emitting element and a phosphor film which is formed on an internal surface of the sealing structure. The sealing structure includes a blocking portion which is formed integrally with the substrate so as to surround the light emitting element on the substrate and functions as a reflector that reflects a light emitted from the light emitting element and a cover portion which is arranged on the top of the blocking portion and is bonded to the blocking portion.

Abstract: In an electronic parts packaging structure of the present invention, an electronic parts is mounted or formed on a silicon circuit substrate having a structure in which wiring layers on both sides thereof are connected to each other through a through electrode, and a protruded bonding portion which is ring-shaped and is made of glass, of a seal cap having a structure in which a cavity is constituted by the protruded bonding portion, is anodically bonded to a bonding portion of the silicon circuit substrate, thus, the electronic parts is hermetically sealed in the cavity of the sealing cap.

Abstract: A second substrate 12 is provided above a first substrate 11, and an electronic component 13 is arranged between the first substrate 11 and the second substrate 12 so that between the first substrate 11 and the second substrate 12, the electronic component 13 is sealed and a photosensitive resin 14 having adhesion is provided to bond the first substrate 11 and the second substrate 12 to each other.

Abstract: A method of manufacturing a wiring substrate comprises the steps of attaching a semiconductor chip to a chip positioning plate of a chip tray formed of silicon, executing wiring formation processing using the semiconductor chip attached to the chip positioning plate as a base point, and detaching the wiring-formed wiring substrate from the chip positioning plate. The chip positioning plate comprises a receiving part for receiving the semiconductor chip, and elastic members respectively disposed in two adjacent surfaces of four surfaces constructing an inside surface of the receiving part, and each of these elastic members exerts pressing force toward directions of opposite surfaces, and the semiconductor chip is pinched between each of the opposite surfaces corresponding to each of the elastic members.

Abstract: A light emitting device is disclosed. The light emitting device includes a light emitting element (15), and a light emitting element container (11) having a concave section (20) for containing the light emitting element (15). The concave section (20) includes a side surface (20A) and a bottom surface (20B) almost orthogonal to the side surface (20A). The light emitting device further includes a conductive paste layer (17) formed of a conductive paste in which metal particles are dispersed in a solution, and the conductive paste layer (17) includes a slanting surface (17A) on the side surface (20A) and the bottom surface (20B).

Abstract: A probe card is disclosed that includes a board having a first surface and a second surface facing away from each other and a through hole formed between the first and second surfaces; and a probe needle having a penetration part and a support part. The penetration part is placed in the through hole without contacting the board and projects from the first and second surfaces of the board. The support part is integrated with a first one of the end portions of the penetration part and connected to one of the first and second surfaces of the board. The support part has a spring characteristic. The penetration part is configured to have a second one of its end portions come into contact with an electrode pad of a semiconductor chip at the time of conducting an electrical test on the semiconductor chip.

Abstract: An interposer includes a substrate made of an inorganic material; a through wiring including conductors embedded in through holes; and an upper wiring and (or)a lower wiring. The through wiring, the upper wiring and the lower wiring are respectively formed on preliminary wiring patterns that are additionally simultaneously or sequentially formed on layers made of an insulating material applied to at least wiring forming parts of the substrate, and are formed with a metal mold itself used for forming the preliminary wiring patterns or layers made of a wiring material applied by a printing operation, a plating operation or a deposition on the preliminary wiring patterns formed on the layers of the insulating material by transferring a fine structure pattern of the metal mold.

Abstract: In a method of manufacturing a semiconductor device having a through electrode 56 that connects an electrode pad 20 of a semiconductor element 14, which has a device forming layer 18 and the electrode pad 20 on one surface side, and a rewiring pattern 52 on other surface side of the semiconductor element 14, the device forming layer 18 and the electrode pad 20 are formed on an upper surface side of the semiconductor element 14, a first resist layer 62 is formed on surfaces of the electrode pad 20 and the device forming layer 18, an opening 64 is formed in the electrode pad 20 by the etching, and a through hole 54 is formed in the semiconductor element 14 by the etching in a position that is communicated with the opening 64. The device forming layer 18 is protected by the first resist layer 62, and also a flip-chip connection can be applied by providing the through electrode 56 to attain a downsizing.