Semiconductor device having vertical metal insulator semiconductor transistors having plural spatially overlapping regions of different conductivity type
A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-395558, filed Dec. 27, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a substrate structure of a semiconductor device having vertical power MISFETs (Metal Insulator Field Effect Transistors) each having a gate electrode formed on a semiconductor substrate, as well as a method of manufacturing this substrate structure.
2. Description of the Related Art
In a vertical power MIS (including a MOS (Metal Oxide Semiconductor) FET formed on a semiconductor substrate, a drain current flows between a source and drain electrodes formed on a top and bottom surfaces, respectively, of a semiconductor substrate. Such an element allows the resistance of a current passage to be reduced and is thus often used as a power device.
Second P base areas 106, which contact with the first P base areas 103, are formed under a surface of the second semiconductor substrate. Reference numerals 107, 108, 109, and 110 denote an N source area, a gate insulating film, a gate area, and a source area.
The width of the P base area 103 and the N− drain area 102 located between the P base areas 103 (a P and N type pillar layers, respectively) and the amounts of P and N type impurities contained in these areas are optimally designed. Thus, if a reverse bias voltage is applied to the MISFET, the P and N type pillar layers are depleted. This structure enables on resistance to be reduced compared to other vertical MISFETs.
Other known examples of a MISFET improved so as to reduce the on resistance is described in U.S. Pat. No. 5,216,275 and Jpn. Pat. Appln. KOKAI Publication No. 2000-40822. In this U.S. Patent, pillar-like P-type areas 7 (corresponding to 103 in
The structure shown in
A MISFET having the structure shown in
Further, the manufacturing costs can be cut down by reducing the number of epitaxial growth layers. However, in this case, the diffusion areas 120 must be enlarged as shown in
The present invention is provided in view of these circumstances. It is an object of the present invention to provide a semiconductor device having a drift area structure with a reduced pitch between each area (P type area) exhibiting the same polarity as that of a P type and a corresponding area (N type area) exhibiting the same polarity as that of an N type and terminal area structure, in order to form MISFET elements having a fine structure and achieve complete depletion.
BRIEF SUMMARY OF THE INVENTIONAccording to a first aspect of the present invention, there is provided a semiconductor device comprising a semiconductor layer of a first conductive type and a diffusion area formed the semiconductor layer, the diffusion area comprising first impurity diffusion areas of the first conductive type and second impurity diffusion areas of a second conductive type which are alternately formed, the diffusion area having first areas of the first conductive type and second areas of the second conductive type which are defined by the impurity concentrations of the first and second impurity diffusion areas, respectively, wherein a junction between each of the first areas and the corresponding second area is formed in a portion in which the corresponding first and second impurity diffusion areas overlap each other, and the period of the impurity concentration, in a planar direction of the semiconductor layer, of the areas selected from a group consisting of the first and second areas is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the selected areas.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method comprising injecting first impurities of a first conductive type and second impurities of a second conductive type into a surface of a semiconductor layer of a first conductive type; and diffusing the first and second impurities to form a diffusion area, the diffusion area having a first area and a second area, the first and second areas defined by an impurity concentration of a first impurity diffusion area of the first conductive type and a second impurity diffusion area of the second conductive type, the first and second impurity diffusion area overlapping each other, and a period of the impurity concentration, in a planar direction of the semiconductor layer, of an area selected from a group consisting of the first and second areas being smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the selected areas.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
FIGS. 6 to 9 are diagrams illustrating first and second diffusion layers 13 and 14, shown in
FIGS. 14 to 16 are diagrams illustrating first and second diffusion layers 13 and 14, shown in
FIGS. 34 to 36 are sectional views of a conventional vertical MISFET; and
Embodiments of the present invention will be described below with reference to the drawings. In the description below, components having substantially the same functions and configurations are denoted by the same reference numerals. Duplicate description will be given only when required.
First EmbodimentA first embodiment will be described with reference to FIGS. 1 to 12.
As shown in
An N+ drain area 11 is formed in the first semiconductor substrate 1. The N+ drain area 11 is connected to a drain area 20 formed on a back surface of the first semiconductor substrate 1.
An N− drain area 12 which contacts with the N+ drain area 11 is formed in the second semiconductor substrate 2. An impurity diffusion area is formed in the N− drain area 12 by diffusing impurities and has an impurity concentration higher than that of the second semiconductor substrate 2. This impurity diffusion area is composed of first diffusion areas 13 and second diffusion areas 14 formed inside the first diffusion area 13. The first diffusion areas 13 have the same polarity as that of the N type. The second diffusion areas 14 have the same polarity as that of the P type. The end of each of the second diffusion areas 14 is adjacent to the corresponding first diffusion area 13. The junction between each of the first diffusion areas 13 and the corresponding second diffusion area 14 in a substrate planar direction is perpendicular to the substrates.
N and P type impurities are mixed in the first and second diffusion areas 13 and 14. In each portion of the impurity diffusion area, the concentrations of these impurities define the first or second diffusion areas 13 or 14 as described below in detail. There are differences in impurity concentration among the portions of the first and second diffusion areas 13 and 14. However, in terms of an average value, the impurity concentration of the second semiconductor substrate 2 is set to be greatly lower than those of the first and second diffusion areas 13 and 14. More specifically, the impurity concentrations are set so that the concentration in the second semiconductor substrate is equal to or smaller than one-fifths of those in the first and second diffusion areas 13 and 14. Preferably, the concentration in the second semiconductor area 2 is one-two-hundredth to one-fifth and more preferably one-one-hundredth to one-fifth of those in the first and second diffusion areas.
The first diffusion areas 13 each function as an N drain area. The second diffusion areas 14 each function as a first P base area.
Second P base areas 15 are formed on a surface of the semiconductor substrate 10 which is located on the respective first P base area (second diffusion area) 14. The second P base areas 15 are connected to the respective first P base areas 14 and formed by diffusing impurities. N source areas 16 are formed inside each of the P base areas 15. The first diffusion areas 13, the second P base areas 15, and the N source areas 16 are exposed from a main surface of the semiconductor substrate 10 (the N− drain areas 12 is normally passivated by an oxide film).
Gate electrodes 18 are each formed on the main surface of the semiconductor substrate 10 via a gate insulating film 19 such as a silicon oxide film. The gate insulating film 19 and the gate electrode 18 cover a part of the second P base area 15 and areas extending from the second P base area 15 to the N drain area 13 and the N source area 16. Source-base leader electrodes (hereinafter referred to as “source electrodes”) 17 are formed on the main surface of the semiconductor substrate 10. The source electrodes 17 each have a central portion formed on the P base area 15 and opposite ends each covering a part of the N source area 16.
Now, the first and second diffusion areas 13 and 14 will be described below in detail with reference to FIGS. 6 to 9. FIGS. 6 to 9 illustrate the first and second diffusion layers 13 and 14 in
Then, as shown in
Then, as shown in
The period “a” substantially corresponds to the period of concentration of the impurities in the first or second diffusion area 13 or 14, or the pitch of the diffusion areas 13 or 14, or the spacing between the phosphorous or boron injection areas 32 or 31. These descriptions also apply to the P concentration profile. The junctions 35 are each formed at the position where the phosphorous (P) concentration profile equals the boron (B) concentration profile.
The boron injection areas 31 and the phosphorous injection areas 32 are formed, for example, under the above described conditions. As a result, the period “a” of the boron diffusion areas 33 and phosphorous diffusion areas 34 is smaller than the maximum diffusion length (diffusion width) of the individual diffusion areas 33 and 34 in the substrate planar direction. Thus, a high impurity concentration area extends widely in the first and second diffusion areas 13 and 14.
The high impurity concentration area extending widely will now be explained with examples.
As shown in
According to the first embodiment, the first and second diffusion areas 13 and 14 are formed in the second semiconductor substrate 2 with a low impurity concentration, using impurities formed by ion injection and diffusion. The first and second diffusion areas 13 and 14 are defined by the concentrations and overlapping portions in the second substrate 2. Thus, the first and second diffusion areas 13 and 14 can be formed to be narrower while avoiding joining the adjacent second diffusion areas 14 together. This serves to provide a semiconductor device with reduced on resistance.
According to the first embodiment, the period a of impurity concentration of each of the first and second diffusion areas 13 and 14 is smaller than the maximum diffusion length of the boron diffusion areas 33 and phosphorous diffusion areas 34 in the substrate planar direction. Thus, junction 35 is formed at the vicinity of the center of the boron diffusion areas 33 and phosphorous diffusion areas 34. As a result, most part of the first and second diffusion layers 13 and 14 are formed at the vicinity of the center of the phosphorous diffusion areas 34 and the boron diffusion areas 33, and this part has a high impurity concentration. Thus, the impurity concentration of the first diffusion areas 13, which constitute a current passage, is high while the MISFET is on. This serves to provide a semiconductor device with reduced on resistance. Further, narrow width (small period “a”) of the first and second diffusion layers 13 and 14 help these diffusion layers 13 and 14 deplete completely. This serves to provide a semiconductor device with a high withstand voltage, while reducing a cell pitch.
Further, the balance of total sum of impurity concentrations in the first and second diffusion areas 13 and 14 is important to obtain a high withstand voltage. According to the present application, adding an N type dopant during epitaxial growth conventionally forms N type impurities corresponding to the first diffusion areas 13. On the other hand, an ion injection forms the first and second diffusion areas 13 and 14 in the first embodiment. The ion injection improves concentration controllability, thus allowing the balance to be maintained easily even with finer design.
Second EmbodimentA second embodiment will be described with reference to FIGS. 13 to 20. In the first embodiment, the second semiconductor substrate 2 is composed of, for example, a single epitaxial growth layer or the like. In contrast, a semiconductor device according to the second embodiment has a structure in which the second semiconductor substrate 2 has a plurality of layers and in which PN junctions are formed to be deeper by repeating the manufacturing method of the first embodiment.
Now, with reference to
As shown in
The thermal treatment makes the first and second diffusion layers 13 and 14 from the phosphorous diffusion areas 34 and the boron diffusion areas 33. PN junctions are formed in the semiconductor substrate 10 in the vertical direction.
Further, in
L>a (1)
r>b/2 (2)
Now, the diffusion structure of the second semiconductor substrate 2 will be described with reference to FIGS. 17 to 20.
The N type impurity concentration is higher than the P type impurity concentration in this area, and the area exhibits the first diffusion area 13 which has the same polarity as that of the N type. As shown in
Now, description will be given below of a comparison of the second embodiment with a conventional example.
As described in the first embodiment, narrowing the first and second diffusion layers 13 and 14 can increase the impurity concentrations of these diffusion layers 13 and 14, and thus the on resistance can be reduced. This is shown in
According to the second embodiment, the second semiconductor substrate 2 is configured similarly to the first embodiment. Thus, the second embodiment produces effects similar to those of the first embodiment.
Further, the second embodiment 2 has a structure in which a plurality of epitaxial layers are stacked together a number of times. Furthermore, the concentration period “a” of each first diffusion area 13 or second diffusion area 14 in the substrate planar direction is greater than the concentration period “b” (the thickness of a single epitaxial layer) in the substrate depth direction (a>b). This also serves to increase the impurity concentrations of the first and second diffusion areas 13 and 14 and provide a semiconductor device with a high withstand voltage and reduced on resistance, as in the first embodiment. It is noted that the advantages brought about by the second embodiment can be obtained while the relationship between “a” and “b” is a<b. However, design and implementation can be performed easily when the relationship is a>b than a<b.
Further, the second semiconductor substrate 2 having such characteristics has a structure in which a plurality of epitaxial layers are stacked together a number of times. Thus, if a semiconductor device is formed with the same epitaxial number as that in the conventional example, about half the on resistance is obtained compared to the conventional example. On the other hand, the same on resistance can be accomplished using half the epitaxial number compared to the conventional example.
Third EmbodimentA third embodiment will be described with reference to FIGS. 22 to 24. In addition the structure of the second embodiment, the third embodiment has a structure in which diffusion areas are further repeatedly formed breadthwise.
According to the third embodiment, the second embodiment 2 and the first and second diffusion areas 13 and 14 are structured similarly to the second embodiment. Thus, the third embodiment produces effects similar to those of the first and second embodiments.
Furthermore, according to the third embodiment, three or more second diffusion areas 14 are formed. Thus, the MISFET elements can be formed with a high density. This provides a semiconductor device that can be highly integrated.
Fourth EmbodimentA fourth embodiment relates to a structure used in addition to those of the first to third embodiments, and is directed to a terminal structure of a semiconductor device. As described above, according to the first to third embodiments of the present invention, the concentration of the second semiconductor substrate 2 can be maintained at a low level. This is because, injecting ions into an N type semiconductor substrate with a low concentration makes N and P type pillar-like diffusion layers as opposed to injecting P type impurities into an N type semiconductor substrate with a high concentration in the conventional example.
As shown in
An N+ stopper layer 42 with a high concentration is formed at the end of the semiconductor device and on the surface of the second semiconductor substrate 2. An N+ stopper electrode 43 is formed on the N+ stopper layer 42. An insulating film (interlayer film) 44 is formed in the terminal area of the semiconductor device and on the surface of the second semiconductor substrate 2.
The effects of the fourth embodiment will be described below. In the terminal area of the semiconductor device, a depletion layer must be formed to an appropriate extent in order to obtain a withstand voltage in this area. However, if a semiconductor layer (corresponding to the second semiconductor substrate 2 in the present embodiments) provided with N and P type diffusion layers has a high concentration as in the prior art, a depletion layer extending to the terminal is not sufficiently formed. Accordingly, separate measures are required in order to sufficiently extend the depletion layer. However, according to the first to third embodiments of the present application, the impurity concentration of the second semiconductor substrate 2 can be reduced. Consequently, it is possible to form a depletion layer extending to the terminal of the semiconductor without any special measures. Thus, when, in addition to such a structure, the guard rings 41 are formed as in the fourth embodiment, a depletion layer can be formed to a larger extent.
According to the fourth embodiment, the second semiconductor substrate 2 and the first and second diffusion layers 13 and 14 are structured similarly to the first to third embodiments. The fourth embodiment thus produces effects similar to those of the first to third embodiments.
Furthermore, according to the fourth embodiment, the terminal area not provided with the first or second diffusion layers 13 or 14 is formed, and the second semiconductor substrate 2, provided with the first and second diffusion layers 13 and 14, have a low impurity concentration. Thus, a depletion layer extending to the terminal of the semiconductor device is formed in this area. This serves to provide a semiconductor device with a high withstand voltage. Furthermore, the formation of the guard rings 41 allows a depletion layer to be formed to a larger extent.
Fifth EmbodimentA fifth embodiment relates to a variation of the fourth embodiment.
According to the fifth embodiment, the second semiconductor substrate 2 and the first and second diffusion layers 13 and 14 are structured similarly to the first to fourth embodiments. The fifth embodiment thus produces effects similar to those of the first to fourth embodiments.
Moreover, according to the fifth embodiment, the insulating film 51, which is thicker toward the end of the semiconductor device, is formed on the surface of the second semiconductor substrate 2. Further, the field plate electrode 52, connected to the source electrode 17 or the gate electrode 18, is formed on the insulating film 51. Thus, electric fields concentrate in a thicker part of the insulating film 51 which is located closer to the end of the field plate electrode 52. The insulating film has a higher withstand voltage than the semiconductor substrate such as silicon, thus serving to provide a semiconductor device having a high withstand voltage as a whole.
Sixth EmbodimentAs described above, for a semiconductor device in which a semiconductor layer (corresponding to the second semiconductor substrate 2 in the present embodiments) provided with N and P type diffusion layers has a high concentration, measures are required in order to sufficiently form a depletion layer extending to the terminal of the semiconductor device. One possible method for this purpose is to form an impurity diffusion layer in the semiconductor layer which does not function as a MISFET.
In the terminal area of a semiconductor device configured as described above, depletion layers are formed along the junctions between the third diffusion layers 61 and the fourth diffusion layers 62. Accordingly, in the planar breadthwise direction and a depth direction of the semiconductor substrate, depletion layers are formed so as to correspond to the positions at which the third and fourth diffusion layers 61 and 62 are formed. In this regard, the planar shapes of the third and fourth diffusion layers 61 and 62 (the shapes in
Now, the effects of the sixth embodiment will be described. In the present embodiments, which allow the maintenance of impurity concentration of the second semiconductor substrate 2 at a low level, a common structure such as the one shown in the fourth and fifth embodiments is used to obtain the desired withstand voltage. However, if such a method still fails to form depletion layers to a sufficient extent, the sixth embodiment can be effectively applied.
Furthermore, the impurity concentration of the second semiconductor substrate 2 can be reduced, so that the concentration of impurities can be controlled more easily than in the case in which impurity diffusion layers are formed in a semiconductor substrate with a high impurity concentration.
According to the sixth embodiment, the second semiconductor substrate 2 and the first and second diffusion layers 13 and 14 are structured similarly to the first to fourth embodiments. The sixth embodiment thus produces effects similar to those of the first to fourth embodiments.
According to the sixth embodiment, furthermore, the third and fourth diffusion layers 61 and 62, which are used to form depletion layers, are formed inside the second semiconductor substrate 2 with a low impurity concentration. Thus, the third and fourth diffusion layers 61 and 62 can be formed easily and depletion layers can be formed to a larger extent, which serves to provide a semiconductor device with a high withstand voltage.
Further, the third and fourth diffusion layers 61 and 62 can be formed when the first and second diffusion layers 13 and 14 are formed at the same time. Therefore, a semiconductor device with a high withstand voltage can be obtained by fewer manufacturing steps than ones in the fourth and fifth embodiments.
Seventh EmbodimentA seventh embodiment relates to a variation of the sixth embodiment.
The third and fourth diffusion layers 61 and 62 are formed to meet the following equation:
0.5<(S1×Qd1)/(S2×Qd2)<1.5 (3)
where Qd1: dose of impurities used when ions are injected to form the third diffusion layers 61,
Qd2: dose of impurities used when ions are injected to form the fourth diffusion layers 62,
S1: area in which ions are injected to form the third diffusion layers 61, and
S2: area in which ions are injected to form the fourth diffusion layers 62.
By forming the third and fourth diffusion layers 61 and 62 so as to meet Equation (3), depletion layers are extended far from the junctions between the diffusion layers 61 and the diffusion layers 62. Thus, the third and fourth diffusion layers 61 and 62 may be formed, for example, like a lattice as shown in
According to the seventh embodiment, the second semiconductor substrate 2 and the first and second diffusion layers 13 and 14 are structured similarly to the first to fourth embodiments. The seventh embodiment thus produces effects similar to those of the first to fourth embodiments.
Furthermore, according to the seventh embodiment, the third and fourth embodiments 61 and 62, used to form depletion layers, are formed radially or like a lattice under the predetermined conditions. Depletion layers can be formed to a large extent in the terminal area. This serves to provide a semiconductor device with a high withstand voltage.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Claims
1. (canceled)
2. A method of manufacturing a semiconductor device comprising:
- injecting first impurities of a first conductive type and second impurities of a second conductive type into a surface of a first semiconductor layer of a first conductive type at a plurality of points; and
- diffusing the first and second impurities to form a first diffusion area of the first conductive type and a second diffusion area of the second conductive type, the first diffusion area and the second diffusion area being defined by a first concentration profile of the first impurities and a second concentration profile of the second impurities, a junction between the first diffusion area and the second diffusion area being formed where a concentration of the first impurities and a concentration of the second impurities are same, a period of the first concentration profile in a planar direction of the first semiconductor layer being smaller than a maximum diffusion width of the first impurities in the planar direction of the first semiconductor layer.
3. The method according to claim 2, further comprising:
- forming a second semiconductor layer of the first conductive type on the first semiconductor layer after injecting the first and second impurities into the first semiconductor layer;
- injecting third impurities of the first conductive type into the second semiconductor layer over points where the first impurities are injected in the first semiconductor layer; and
- injecting fourth impurities of the second conductive type into the second semiconductor layer over points where the second impurities are injected in the first semiconductor layer, wherein
- diffusing the first and second impurities further includes diffusing the first to fourth impurities until the first diffusion area and the second diffusion area extend over the first semiconductor layer and the second semiconductor layer.
4. The method according to claim 2, wherein the first impurities include phosphorous and the second impurities include boron.
5. The method according to claim 3, wherein the first impurities and the third impurities include phosphorous and the second impurities and the fourth impurities include boron.
6. A method of manufacturing a semiconductor device comprising:
- injecting first impurities of a first conductive type into a first semiconductor layer of the first conductive type at least at two first points;
- injecting second impurities of a second conductive type into the first semiconductor layer between the two first points; and
- diffusing the first impurities and the second impurities until a first concentration profile of the first impurities having a first period and a second concentration profile overlap to form a first diffusion area and a second diffusion area which are defined by the first concentration profile and the second concentration profile, the first period being smaller in a planar direction of the first semiconductor layer than a maximum diffusion width of the first impurities.
7. The method according to claim 6, wherein the first impurities include phosphorous and the second impurities include boron.
8. The method according to claim 6, further comprising forming the first semiconductor layer by epitaxial growth above a semiconductor substrate before injecting the first impurities and the second impurities, the first semiconductor layer having an impurity concentration equal to or less than a fifth of an impurity concentration of the first diffusion area.
9. The method according to claim 6, further comprising:
- forming a second semiconductor layer of the first conductive type on the first semiconductor layer after injecting the first impurities and the second impurities into the first semiconductor layer;
- injecting third impurities of the first conductive type into the second semiconductor layer over points where the first impurities are injected in the first semiconductor layer; and
- injecting fourth impurities of the second conductive type into the second semiconductor layer over points where the second impurities are injected in the first semiconductor layer, wherein diffusing the first impurities and the second impurities further includes diffusing the first to fourth impurities until the first diffusion area and the second diffusion area extend over the first semiconductor layer and the second semiconductor layer.
10. The method according to claim 9, wherein the first impurities and the third impurities include phosphorous and the second impurities and the fourth impurities include boron.
11. The method according to claim 9, further comprising forming the first semiconductor layer by epitaxial growth above a semiconductor substrate before injecting the first impurities and the second impurities, the first semiconductor layer having an impurity concentration equal to or less than a fifth of an impurity concentration of the first diffusion area, wherein
- forming a second semiconductor layer includes forming by epitaxial growth the second semiconductor layer having an impurity concentration equal to or less than a fifth of an impurity concentration of the first diffusion area.
12. The method according to claim 6, wherein
- injecting the first impurities includes injecting the first impurities at a plurality of points,
- injecting the second impurities includes injecting the second impurities at a plurality of points between the plurality of points where the first impurities are injected,
- the second concentration profile has a second period which is smaller in the planar direction of the first semiconductor layer than a maximum diffusion width of the second impurities, and
- plural of said first diffusion area and said second diffusion area are formed in the first semiconductor layer.
13. The method according to claim 6, wherein the plurality of points where the first impurities are injected are apart from each other at 6 to 18 μm and the plurality of points where the second impurities are injected are apart from each other at 6 to 18 μm.
14. The method according to claim 6, further comprising forming a third diffusion area in an end region which is formed between an end of an first semiconductor layer and a MISFET region where the plural of the first diffusion area and the plural of the second diffusion area are formed.
15. The method according to claim 6, further comprising:
- forming a base area of the second conductive type in a surface of the first semiconductor layer and connected to the second diffusion area;
- forming a source area of the first conductive type in the base area;
- forming a source electrode on the surface of the first semiconductor layer so as to cover a part of the source area;
- forming a gate electrode on the surface of the first semiconductor layer with a gate insulating film interposed therebetween so as to cover a part of the base area, source area, and first diffusion area;
- forming an insulating film in the end region and on the surface of the first semiconductor layer, the insulating film having a height increasing toward the end of the first semiconductor layer; and
- forming a first electrode on the insulating film, the first electrode being connected to the source electrode or the gate electrode.
16. The method according to claim 6, further comprising forming a third diffusion area and a fourth diffusion area having substantially a same structure as the first diffusion area and the second diffusion area, respectively, in an end region which is formed between an end of an first semiconductor layer and a MISFET region where a plural of the first diffusion area and a plural of the second diffusion area are formed
17. The method according to claim 6, wherein the third diffusion area and the fourth diffusion area meet: 0.5<(S1×Qd1)/(S2×Qd2)<1.5
- where Qd1: dose of impurities used when ions are injected to form the third diffusion area,
- Qd2: dose of impurities used when ions are injected to form the fourth diffusion area,
- S1: area in which ions are injected to form the third diffusion area, and
- S2: area in which ions are injected to form the fourth diffusion area.
18. The method according to claim 16, wherein the third diffusion area and the fourth diffusion area are formed to be substantially linear in a plane of the first semiconductor layer.
19. The method according to claim 16, wherein the third diffusion area and the fourth diffusion area are formed to be substantially radial in a plane of the first semiconductor layer.
20. The method according to claim 16, wherein the third diffusion area and the fourth diffusion area form a substantial lattice in a plane of the first semiconductor layer.
21. A method of manufacturing a semiconductor device comprising:
- forming a first semiconductor layer by epitaxial growth on a semiconductor substrate;
- injecting first impurities of the first conductive type and second impurities of a second conductive type into the first semiconductor layer, points where the first impurities are injected and points where the second impurities are injected being apart from each other;
- conducting formation of an i-th semiconductor layer on the (i−1)-th semiconductor layer by epitaxial growth and i-th injection of the first impurities and the second impurities into the i-th semiconductor layer over points where the first impurities and the second impurities are injected in the (i−1)-th semiconductor layer respectively, i being a natural number at least two, a set of the formation of an i-th semiconductor layer and the i-th injection being repeated with i=i+1 for every set until n-th semiconductor layer is formed and n-th injection is conducted, n being a natural number at least two;
- diffusing the first impurities and the second impurities to form a first diffusion area of the first conductive type and a second diffusion area of the second conductive type, the first diffusion area and the second diffusion area extending over the first semiconductor layer to the n-th semiconductor layer, the first diffusion area and the second diffusion area being defined by a first concentration profile of the first impurities and a second concentration profile of the second impurities, a junction between the first diffusion area and the second diffusion area being formed where a concentration of the first impurities and a concentration of the second impurities are same.
22. The method according to claim 21, wherein the first impurities include phosphorous and the second impurities include boron.
23. The method according to claim 21, wherein the first semiconductor layer to the n-th semiconductor layer have an impurity concentration equal to or less than a fifth of an impurity concentration of the first diffusion area.
Type: Application
Filed: Dec 6, 2005
Publication Date: Jul 6, 2006
Inventors: Hideki Okumura (Yokohama-shi), Hitoshi Kobayashi (Yokohama-shi), Masanobu Tsuchitani (Kawasaki-shi), Akihiko Osawa (Himeji-shi), Wataru Saito (Kawasaki-shi), Masakazu Yamaguchi (Kawasaki-shi), Ichiro Omura (Yokohama-shi)
Application Number: 11/294,411
International Classification: H01L 29/00 (20060101); H01L 21/425 (20060101); H01L 21/336 (20060101);