Patents by Inventor Masaki Shiraishi

Masaki Shiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080180974
    Abstract: A technique for suppressing lowering of withstand voltage and lowering of breakdown resistance and reducing a feedback capacitance of a power MISFET is provided. A lateral power MISFET that comprises a trench region whose insulating layer is formed shallower than an HV-Nwell layer is provided in the HV-Nwell layer (drift region) formed on a main surface of a semiconductor substrate in a direction from the main surface to the inside. The lateral power MISFET has an arrangement on a plane of the main surface including a source layer (source region) and a drain layer (drain region) arranged at opposite sides to each other across a gate electrode (first conducting layer), and a dummy gate electrode (second conducting layer) that is different from the gate electrode is arranged between the gate electrode and the drain layer.
    Type: Application
    Filed: December 27, 2007
    Publication date: July 31, 2008
    Applicant: Renesas Technology Corp.
    Inventors: Masaki Shiraishi, Noboru Akiyama, Takayuki Hashimoto
  • Publication number: 20080154561
    Abstract: A method for modeling a tire model used for a computer simulation of a pneumatic tire with a toroidal main body and a circumferentially extending tread pattern formed thereon, comprises a step for setting a three-dimensional main body model by dividing the main body by N (N is an integer not less than 2) equally in a circumferential direction of the tire using a finite number of elements a step for setting a three-dimensional pattern model by dividing the tread pattern by M (M is an integer greater than N) equally in the circumferential direction of the tire using a finite number of elements to make, a step for coupling the pattern model with the main body model while aligning each tire rotation axis to make a three-dimensional tire model, and a correcting step for moving nodal points existing on a radially outer surface of the pattern model such that a thickness of the pattern model measured from a radially outer surface of the main body model in a normal direction becomes constant.
    Type: Application
    Filed: November 6, 2007
    Publication date: June 26, 2008
    Inventor: Masaki Shiraishi
  • Patent number: 7343788
    Abstract: A method for tire rolling simulation on sand comprises the steps of modeling a tire using finite elements to build a tire model, modeling a sandy road using finite volumes to build a sandy road model which can exhibit elastoplasticity with both elastic and plastic properties, and executing a numerical simulation in which the tire model is made to roll on the sandy road model in a predetermined condition.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: March 18, 2008
    Assignee: Sumitomo Rubber Industries, Ltd.
    Inventors: Masahiro Kishida, Masaki Shiraishi
  • Publication number: 20080023758
    Abstract: The object of the present invention is to reduce parasitic inductance of a main circuit in a power supply circuit. The present invention provides a non-insulated DC-DC converter having a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOS•FET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.
    Type: Application
    Filed: September 28, 2007
    Publication date: January 31, 2008
    Inventors: Masaki Shiraishi, Noboru Akiyama, Tomoaki Uno, Nobuyoshi Matsuura
  • Patent number: 7308390
    Abstract: A method and an apparatus for estimating tire/wheel performance by simulation is disclosed, wherein a tire/wheel assembly model of an assembly of a wheel and a tire mounted thereon is made, and a simulation of the tire/wheel assembly model rolling under a given condition is carried out to obtain an estimated data indicating performance or a characteristic of the tire, wheel or the assembly. Preferably, the tire/wheel assembly model is made through a simulation of mounting a tire model on a wheel model, taking a friction into consideration. Also, the rolling simulation is carried out taking a friction between the tire beads and wheel rim into consideration.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: December 11, 2007
    Assignee: Sumitomo Rubber Industries, Ltd.
    Inventor: Masaki Shiraishi
  • Publication number: 20070278516
    Abstract: The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETS, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.
    Type: Application
    Filed: May 30, 2007
    Publication date: December 6, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Takayuki Hashimoto, Noboru Akiyama, Masaki Shiraishi, Tetsuya Kawashima
  • Patent number: 7295453
    Abstract: The object of the present invention is to reduce parasitic inductance of a main circuit in a power supply circuit. The present invention provides a non-insulated DC-DC converter having a circuit in which a power MOS• FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOS•FET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: November 13, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Masaki Shiraishi, Noboru Akiyama, Tomoaki Uno, Nobuyoshi Matsuura
  • Patent number: 7280951
    Abstract: A method of making a finite element model of a tire is disclosed. The tire is provided in a tread portion with a fine groove having a dead end including at least the bottom. The tread portion is divided into elements so that the elements include first elements on one side of the fine groove and second elements on the other side of the fine groove, and the first elements and second elements have nodes in common at the dead end, but the first elements and second elements do not have nodes in common at other positions than the dead end.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: October 9, 2007
    Assignee: Sumitomo Rubber Industries, Ltd.
    Inventor: Masaki Shiraishi
  • Publication number: 20070200537
    Abstract: A power supply capable of reducing loss of large current and high frequency. In an MCM for power supply in which a high-side power MOSFET chip, a low-side power MOSFET chip and a driver IC chip driving them are sealed in one sealing material (a capsulating insulation resin), a wiring length of a wiring DL connecting an output terminal of the driver IC chip to a gate terminal of the low-side power MOSFET chip or a source terminal is made shorter than a wiring length of a wiring DH connecting the output terminal of the driver IC chip to a gate terminal of the high-side power MOSFET chip or a source terminal. Further, the number of the wiring DL is made larger than the number of the wiring DH.
    Type: Application
    Filed: January 19, 2007
    Publication date: August 30, 2007
    Inventors: Noboru Akiyama, Takayuki Hashimoto, Masaki Shiraishi, Tetsuya Kawashima, Koji Tateno, Nobuyoshi Matsuura
  • Publication number: 20070195563
    Abstract: In a non-isolated DC/DC converter, a reference potential for a low-side pre-driver which drives a gate of a low-side MOSFET is applied from a portion except for a main circuit passing through a high-side MOSFET and the low-side MOSFET so that a parasitic inductance between a source of the low-side MOSFET and the pre-driver is increased without increasing the sum of parasitic inductances in the main circuit and negative potential driving of the gate of the low-side MOSFET can be performed and a self turn-on phenomenon can be prevented without adding any member and changing drive system.
    Type: Application
    Filed: January 19, 2007
    Publication date: August 23, 2007
    Inventors: Masaki Shiraishi, Takayuki Hashimoto, Noboru Akiyama
  • Patent number: 7254492
    Abstract: A method of computing an energy loss generated in a viscoelastic material, including analyzing a dynamic behavior of a to-be-analyzed object composed of the viscoelastic material by a numerical analysis method; and computing the energy loss of the object momently when the object makes the dynamic behavior by a viscous component of the object. The energy loss computed by the energy loss computing method is visualized by a golf ball-hitting simulation to momently evaluate the energy loss generated in the golf ball.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: August 7, 2007
    Assignee: SRI Sports Limited
    Inventors: Kazuyoshi Miyamoto, Masaki Shiraishi
  • Publication number: 20070145580
    Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.
    Type: Application
    Filed: March 1, 2007
    Publication date: June 28, 2007
    Inventors: Yukihiro SATOU, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
  • Publication number: 20070137290
    Abstract: A method for pneumatic tire simulation comprises the steps of modeling a tire body having a cavity extending in a circumferential direction of the tire using finite elements to build a tire body model, modeling the cavity surrounded by the tire body using finite volumes to build a cavity model, setting a pneumatic tire model coupled the tire body model with the cavity model so that a relative distance between an outer surface of the cavity model and an inner surface of the tire body model does not change, modeling a road using finite elements to build a road model, and executing a numerical simulation in which the tire model is made to roll on the road model in a predetermined condition.
    Type: Application
    Filed: December 8, 2006
    Publication date: June 21, 2007
    Inventor: Masaki Shiraishi
  • Publication number: 20070120194
    Abstract: A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 ?m or less, a p? type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p? type semiconductor region is formed under a n+ type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.
    Type: Application
    Filed: January 25, 2007
    Publication date: May 31, 2007
    Inventors: Masaki Shiraishi, Yoshito Nakazawa
  • Publication number: 20070107506
    Abstract: A method for tire rolling simulation on sand comprises the steps of modeling a tire using finite elements to build a tire model, modeling a sandy road using finite volumes to build a sandy road model which can exhibit elastoplasticity with both elastic and plastic properties, and executing a numerical simulation in which the tire model is made to roll on the sandy road model in a predetermined condition.
    Type: Application
    Filed: October 20, 2006
    Publication date: May 17, 2007
    Applicant: Sumitomo Rubber Industries, Ltd.
    Inventors: Masahiro Kishida, Masaki Shiraishi
  • Publication number: 20070090814
    Abstract: A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced.
    Type: Application
    Filed: October 24, 2006
    Publication date: April 26, 2007
    Inventors: Takayuki Hashimoto, Nobuyoshi Matsuura, Masaki Shiraishi, Yukihiro Satou, Tetsuya Kawashima
  • Publication number: 20070045727
    Abstract: A technology capable of realizing a MOSFET with low ON-resistance and low feedback capacitance, in which the punch through of a channel layer can be prevented even when the shallow junction of the channel layer is formed in a planar type MOSFET is provided. A P type polysilicon is used for a gate electrode in a planar type MOSFET, in particular, in an N channel DMOSFET.
    Type: Application
    Filed: August 24, 2006
    Publication date: March 1, 2007
    Inventors: Masaki Shiraishi, Takayuki Iwasaki, Nobuyoshi Matsuura, Yoshito Nakazawa, Tsuyoshi Kachi
  • Publication number: 20070013000
    Abstract: In a low withstand voltage vertical trench MOSFET having an SJ structure, an N type epitaxial layer which is a current path and a trench structure which extends from a semiconductor surface into the N type epitaxial layer are provided, and a floating P type region is formed in a portion of the N type epitaxial layer positioned below the trench structure. The P type region is formed below the trench structure by ion-implanting P type impurity ions. By forming the P type region below a fine trench gate through ion-implantation, energy for ion-implantation can be reduced, and a fine SJ structure can be fabricated. Accordingly, a device structure which allow formation of a fine SJ structure in a low withstand voltage power MOSFET and a manufacturing method of the same can be provided.
    Type: Application
    Filed: July 12, 2006
    Publication date: January 18, 2007
    Inventor: Masaki Shiraishi
  • Patent number: 7149670
    Abstract: The present invention is a method for tire rolling simulation comprising the steps of: setting a tire model by modeling a tire with the use of elements capable of numerical analysis; setting a road surface model including a road-surface matter model formed by modeling road-surface matter forming a road surface with the use of elements that can be numerically analyzed and can cause a volume change due to compression which is substantially permanent; and performing a tire rolling simulation by making the tire model get in contact with the road-surface matter model, thereby providing the tire model with rotating conditions, and conducting deformation calculations of the tire model and the road-surface matter model at minute time increment intervals.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: December 12, 2006
    Assignee: Sumitomo Rubber Industries, Ltd.
    Inventors: Naoaki Iwasaki, Masaki Shiraishi, Akio Miyori
  • Patent number: 7130748
    Abstract: A simulation method includes the step of momently measuring a value of each of a strain, a strain speed, and a stress generated in the viscoelastic material, deriving time history data of a viscous drag, the strain speed and the stress, thereby deriving a relationship among the strain, the strain speed, and the viscous drag and setting the product as a product model whose performance is analyzed; inputting the relationship to the product model; and computing a stress and strain of a deviation component by using a deviation main strain and a deviation main strain speed converted from an entire coordinate system into a main strain coordinate system and a main strain speed coordinate system respectively to thereby conduct a simulation in consideration of a change of the viscous drag which occurs in dependence of a variation of the strain and the strain speed.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: October 31, 2006
    Assignee: SRI Sports Limited
    Inventors: Masahiko Ueda, Kazuyoshi Miyamoto, Masaki Shiraishi