Patents by Inventor Masaki Shiraishi

Masaki Shiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7130782
    Abstract: A gas flow simulation method includes setting an imaginary object model such as a sphere model having at least one concavity, convexity, groove or projection formed thereon by means of a computer. A spatial part on a periphery of the imaginary object model is set. A surface of the imaginary object model and the spatial part is divided into a large number of blocks to form a large number of latticed divisions by lattice points. A gas flows to the imaginary object model from one direction of the spatial part. A motion element of a flow of the gas in the spatial part for each latticed division or for each latticed point is computed, with the gas flowing in the spatial part and passing along the surface of the imaginary object model. The flow of the gas on the periphery of the imaginary object model is simulated.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: October 31, 2006
    Assignee: SRI Sports Limited
    Inventors: Akio Miyori, Masaki Shiraishi, Kazuhiro Fujisawa, Takahiro Sajima
  • Patent number: 7109577
    Abstract: A power MOS-FET is used as a high side switch transistor for a non-insulated DC/DC converter. An electrode section that serves as a source terminal of the power MOS-FET is connected to one outer lead and two outer leads via bonding wires respectively. The outer lead is an external terminal connected to a path for driving the gate. Each of the outer leads is an external terminal connected to a main current path. Owing to the connection of the main current path and the gate driving path in discrete form, the influence of parasitic inductance can be reduced and voltage conversion efficiency can be improved.
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: September 19, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Masaki Shiraishi, Takayuki Iwasaki, Nobuyoshi Matsuura, Tomoaki Uno
  • Patent number: 7089817
    Abstract: A model (1) is obtained by dividing a golf ball into meshes. The model (1) comprises a large number of elements (3). An outermost layer of the model is wholly formed by fine elements (3a). The outermost layer is wholly formed by a fine element region. A number (Na) of divisions in the fine element region is larger than a number (Nb) of divisions on an inner layer in the fine element region. A ratio (Na/Nb) is 1.1 to 15.0. The fine element (3a) and an element (3b) on the inside of the fine element (3a) are tied to each other. A physical property value of the golf ball is analyzed by a finite element method using the model (1).
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: August 15, 2006
    Assignee: SRI Sports Limited
    Inventors: Masaya Tsunoda, Masaki Shiraishi
  • Publication number: 20060175627
    Abstract: A power supply includes a non-isolated DC-DC converter for use in a power source system having a high side switch and a low side switch, in which HEMT or HFET or gallium nitride device with low capacity and low on-resistance is used for the high side switch and a vertical power MOSFET of silicon device with low on-resistance is used for the low side switch.
    Type: Application
    Filed: February 6, 2006
    Publication date: August 10, 2006
    Inventor: Masaki Shiraishi
  • Patent number: 7066018
    Abstract: A method of simulating a tire rolling on a road includes modeling the tire in finite elements to make a tire model; modeling the surface of the road in finite elements to make a road model; executing a simulation in which the tire model is made to roll on the road model at a predetermined speed; and obtaining information about the tire model. The speed of the tire model is varied by repeating an increase and a decrease based on a predetermined reference speed.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: June 27, 2006
    Assignee: Sumitomo Rubber Industries Ltd.
    Inventors: Kazuyoshi Miyamoto, Masaki Shiraishi
  • Publication number: 20060136151
    Abstract: A method of simulating rolling tire comprises the steps of: modeling the tire in finite elements to make a tire model which comprises a first element having a viscoelastic property; modeling a road in finite elements to make a road model; executing a numerical simulation in which the tire model is made to roll on the road model at a predetermined condition; obtaining six kinds of strains in time sequence from the first element of the tire model with rolling, the six kinds of strains including three kinds of normal strains along a tire meridian direction, a tire circumferential direction and a tire thickness direction, and three kinds of shear strain along the tire meridian direction, the tire circumferential direction and the tire thickness direction; and calculating energy loss of the first element based on the six kinds of the strains.
    Type: Application
    Filed: December 1, 2005
    Publication date: June 22, 2006
    Inventor: Masaki Shiraishi
  • Publication number: 20060113664
    Abstract: The object of the present invention is to reduce parasitic inductance of a main circuit in a power supply circuit. The present invention provides a non-insulated DC-DC converter having a circuit in which a power MOS • FET for a high-side switch and a power MOS • FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS • FET for the high-side switch is formed by a p channel vertical MOS • FET, and the power MOS • FET for the low-side switch is formed by an n channel vertical MOS • FET. Thus, a semiconductor chip formed with the power MOS • FET for the high-side switch and a semiconductor chip formed with the power MOS • FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.
    Type: Application
    Filed: November 29, 2005
    Publication date: June 1, 2006
    Inventors: Masaki Shiraishi, Noboru Akiyama, Tomoaki Uno, Nobuyoshi Matsuura
  • Patent number: 7019362
    Abstract: The gate resistance of a power MOSFET in a semiconductor chip is reduced and the reliability and yield of the gate of the power MOSFET are improved The semiconductor chip includes two or more control electrode pads functioning as control electrodes for a power semiconductor device formed within a semiconductor chip. The two or more control electrode pads are distributed within the periphery of the gate area of the power semiconductor device such that the gate resistance of the power semiconductor device can be reduced. The two or more control electrode pads are connected via bumps or a conductive bonding material to an electrode layer of a multilayer circuit board disposed outside the semiconductor chip.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: March 28, 2006
    Assignee: Renesas Technology, Corp.
    Inventors: Kozo Sakamoto, Takayuki Iwasaki, Masaki Shiraishi
  • Patent number: 7005834
    Abstract: In a power supply of a synchronous rectification type, the self-turn on phenomenon of MOSFET is suppressed without increase of the drive loss to thereby improve the power efficiency. In a synchronous rectifier circuit, a threshold value of a commutation MOSFET is made higher than that of a rectification MOSFET and particularly a threshold value of a commutation MOSFET 3 is made 0.5V or more higher than that of a rectification MOSFET 2. The threshold value of the rectification MOSFET 2 is lower than 1.5V and the threshold of the commutation MOSFET 3 is higher than 2.0V.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: February 28, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Takayuki Iwasaki, Kozo Sakamoto, Masaki Shiraishi, Nobuyoshi Matsuura, Tomoaki Uno
  • Publication number: 20060022298
    Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET GF low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chips and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.
    Type: Application
    Filed: July 29, 2005
    Publication date: February 2, 2006
    Inventors: Masaki Shiraishi, Tomoaki Uno, Nobuyoshi Matsuura
  • Publication number: 20060006432
    Abstract: A semiconductor device in which the self-turn-on phenomenon is prevented that can significantly improve power conversion efficiency. The semiconductor device is a system-in-package for power supply applications in which a high-side switch, a low-side switch, and two drivers are included in a single package. The device includes an auxiliary switch disposed between the gate and source of said low-side switch, and a low-side MOSFET 3 for the low-side switch and an auxiliary MOSFET 4 for the auxiliary switch are disposed on the same chip. In this way, the self-turn-on phenomenon can be prevented, allowing the mounting of a low-side MOSFET 3 with a low threshold voltage and thereby significantly improving power conversion efficiency. The gate of the auxiliary MOSFET 4 is driven by the driver for the high-side MOSFET 2, thereby eliminating the need for a new drive circuit and realizing the same pin configuration as existing products, which facilitates easy replacement.
    Type: Application
    Filed: July 7, 2005
    Publication date: January 12, 2006
    Inventors: Masaki Shiraishi, Takayuki Iwasaki, Nobuyoshi Matsuura
  • Publication number: 20050231990
    Abstract: A non-insulated DC-DC converter a power MOS·FRT for a highside switch and a power MOS·FET for a lowside switch. In the non-insulated DC-DC converter, the power MOS·FET for the highside switch and the power MOS·FET for the lowside switch, driver circuits that control operations of these elements, respectively, and a Schottky barrier diode connected in parallel with the power MOS·FET for the lowside switch are respectively formed in four different semiconductor chips. These four semiconductor chips are housed in one package. The semiconductor chips are mounted over the same die pad. The semiconductor chips are disposed so as to approach each other.
    Type: Application
    Filed: April 19, 2005
    Publication date: October 20, 2005
    Inventors: Tomoaki Uno, Masaki Shiraishi, Nobuyoshi Matsuura, Toshio Nagasawa
  • Publication number: 20050218489
    Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.
    Type: Application
    Filed: February 9, 2005
    Publication date: October 6, 2005
    Inventors: Yukihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
  • Patent number: 6925416
    Abstract: A simulation method of estimating performance of a product made of a viscoelastic material, comprising the steps of measuring a value of a strain, a strain speed, and a stress generated in viscoelastic material momently in a measuring condition equivalent to a state in which the product is actually used; deriving time history data of a viscosity resistance of the viscoelastic material separately in each of a strain increase state and a strain decrease state from time history data of the strain, the strain speed, and the stress and a viscoelastic model set in consideration of a viscosity of the viscoelastic material; setting the product as a product model whose performance is analyzed and inputting a relationship among the strain, the strain speed, and the viscosity resistance to the product model to conduct a simulation in consideration of a phenomenon that the viscosity resistance changes in dependence on a variation of the strain and the strain speed and in consideration of a difference in the viscosity res
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: August 2, 2005
    Assignee: Sumitomo Rubber Industries, Ltd.
    Inventors: Kazuyoshi Miyamoto, Masahiko Ueda, Masaki Shiraishi
  • Publication number: 20050156204
    Abstract: The present invention enhances voltage conversion efficiency of a semiconductor device. In a non-isolated DC-DC converter that includes a high-side switch power MOSFET and a low-side switch power MOSFET, which are series-connected, the high-side switch power MOSFET and driver circuits for driving the high-side and low-side switch power MOSFETs are formed within one semiconductor chip, whereas the low-side switch power MOSFET is formed in another semiconductor chip. The two semiconductor chips are sealed in a single package.
    Type: Application
    Filed: January 10, 2005
    Publication date: July 21, 2005
    Inventors: Tomoaki Uno, Masaki Shiraishi, Nobuyoshi Matsuura, Yukihiro Satou
  • Publication number: 20050086034
    Abstract: The present invention relates to a method of simulating the deformation of a viscoelastic material in which filler is blended to a matrix made of rubber or resin, the method including the steps of dividing the viscoelastic material into a finite number of elements to form a viscoelastic material model, a step of performing deformation calculation of the viscoelastic material model based on a predetermined condition, and a step of acquiring a necessary physical amount from the deformation calculation, where the step of dividing the viscoelastic material into a finite number of elements includes a step of dividing at least one filler into a finite number of elements to form a filler model, and a step of dividing the matrix into a finite number of elements to form a matrix model.
    Type: Application
    Filed: July 23, 2004
    Publication date: April 21, 2005
    Inventors: Masato Naito, Masaki Shiraishi
  • Publication number: 20050029584
    Abstract: A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 ?m or less, a p?type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p?type semiconductor region is formed under a n+type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.
    Type: Application
    Filed: July 8, 2004
    Publication date: February 10, 2005
    Inventors: Masaki Shiraishi, Yoshito Nakazawa
  • Publication number: 20050007078
    Abstract: In a power supply of a synchronous rectification type, the self-turn on phenomenon of MOSFET is suppressed without increase of the drive loss to thereby improve the power efficiency. In a synchronous rectifier circuit, a threshold value of a commutation MOSFET is made higher than that of a rectification MOSFET and particularly a threshold value of a commutation MOSFET 3 is made 0.5V or more higher than that of a rectification MOSFET 2. The threshold value of the rectification MOSFET 2 is lower than 1.5V and the threshold of the commutation MOSFET 3 is higher than 2.0V.
    Type: Application
    Filed: July 2, 2004
    Publication date: January 13, 2005
    Inventors: Takayuki Iwasaki, Kozo Sakamoto, Masaki Shiraishi, Nobuyoshi Matsuura, Tomoaki Uno
  • Publication number: 20050004779
    Abstract: A simulation method includes the step of momently measuring a value of each of a strain, a strain speed, and a stress generated in the viscoelastic material, deriving time history data of a viscous drag, the strain speed and the stress, thereby deriving a relationship among the strain, the strain speed, and the viscous drag and setting the product as a product model whose performance is analyzed; inputting the relationship to the product model; and computing a stress and strain of a deviation component by using a deviation main strain and a deviation main strain speed converted from an entire coordinate system into a main strain coordinate system and a main strain speed coordinate system respectively to thereby conduct a simulation in consideration of a change of the viscous drag which occurs in dependence of a variation of the strain and the strain speed.
    Type: Application
    Filed: July 16, 2002
    Publication date: January 6, 2005
    Inventors: Masahiko Ueda, Kazuyoshi Miyamoto, Masaki Shiraishi
  • Publication number: 20040254745
    Abstract: A simulation method of estimating performance of a product made of a viscoelastic material, comprising the steps of measuring a value of a strain, a strain speed, and a stress generated in viscoelastic material momently in a measuring condition equivalent to a state in which the product is actually used; deriving time history data of a viscosity resistance of the viscoelastic material separately in each of a strain increase state and a strain decrease state from time history data of the strain, the strain speed, and the stress and a viscoelastic model set in consideration of a viscosity of the viscoelastic material; setting the product as a product model whose performance is analyzed and inputting a relationship among the strain, the strain speed, and the viscosity resistance to the product model to conduct a simulation in consideration of a phenomenon that the viscosity resistance changes in dependence on a variation of the strain and the strain speed and in consideration of a difference in the viscosity res
    Type: Application
    Filed: July 9, 2004
    Publication date: December 16, 2004
    Applicant: Sumitomo Rubber Industries, Ltd.
    Inventors: Kazuyoshi Miyamoto, Masahiko Ueda, Masaki Shiraishi