Patents by Inventor Masao Inoue
Masao Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10217872Abstract: A memory cell includes a control gate electrode and a memory gate electrode. The control gate electrode is formed over the upper surface and the sidewall of a fin FA including apart of a semiconductor substrate. The memory gate electrode is formed over one side surface of the control gate electrode and the upper surface and the sidewall of the fin through an ONO film, in a position adjacent to the one side surface of the control gate electrode. Further, the control gate electrode and the memory gate electrode are formed of n-type polycrystalline silicon. A first metal film is provided between the gate electrode and the control gate electrode. A second metal film is provided between the ONO film and the memory gate electrode. A work function of the first metal film is greater than a work function of the second metal film.Type: GrantFiled: June 17, 2017Date of Patent: February 26, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshiyuki Kawashima, Masao Inoue, Atsushi Yoshitomi
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Publication number: 20190013508Abstract: A nonaqueous electrolyte secondary battery includes an electrode assembly including a negative plate and a positive plate including a positive electrode active material mix layer, a nonaqueous electrolyte, a battery case that houses the electrode assembly and the nonaqueous electrolyte, and a pressure-sensitive safety system that operates when the pressure in the battery case reaches a value greater than or equal to a predetermined value. The positive electrode active material mix layer contains lithium carbonate and lithium phosphate. The average particle size of lithium carbonate contained in the positive electrode active material mix layer is greater than the average particle size of lithium phosphate contained in the positive electrode active material mix layer. The number of particles of lithium carbonate contained in the positive electrode active material mix layer is less than the number of particles of lithium phosphate contained in the positive electrode active material mix layer.Type: ApplicationFiled: June 29, 2018Publication date: January 10, 2019Applicant: SANYO Electric Co., Ltd.Inventors: Yuu Takanashi, Masao Inoue, Toyoki Fujihara
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Publication number: 20190013543Abstract: A nonaqueous electrolyte secondary battery includes an electrode assembly including a negative electrode and a positive electrode including a positive electrode active material mix layer containing a lithium-transition metal composite oxide which is a positive electrode active material; a nonaqueous electrolyte; and a battery case that houses the electrode assembly and the nonaqueous electrolyte. The positive electrode active material has a film formed thereon and the film contains 0.04 ?mol to 0.19 ?mol of sulfur per square meter of the specific surface area of particles of the positive electrode active material.Type: ApplicationFiled: June 27, 2018Publication date: January 10, 2019Applicant: SANYO Electric Co., Ltd.Inventors: Yohei Tao, Mio Nosaka, Masao Inoue, Kunihiko Mineya, Akihito Komatsu
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Publication number: 20180308964Abstract: The present invention makes it possible, in a manufacturing process of a semiconductor device, to inhibit: impurities from diffusing from a substrate to a semiconductor layer; and the withstand voltage of a transistor from deteriorating. In the present invention, a first electrically conductive type epitaxial layer is formed over a first electrically conductive type base substrate. The impurity concentration of the epitaxial layer is lower than that of the base substrate. A second electrically conductive type first embedded layer and a second electrically conductive type second embedded layer are formed in the epitaxial layer. The second embedded layer is deeper than the first embedded layer, is kept away from the first embedded layer, and has an impurity concentration lower than the first embedded layer. A transistor is further formed in the epitaxial layer.Type: ApplicationFiled: June 26, 2018Publication date: October 25, 2018Inventors: Masaru Kadoshima, Masao Inoue
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Publication number: 20180308991Abstract: To improve the performance of a semiconductor device, the semiconductor device includes an insulating film portion over a semiconductor substrate. The insulating film portion includes an insulating film containing silicon and oxygen, a first charge storage film containing silicon and nitrogen, an insulating film containing silicon and oxygen, a second charge storage film containing silicon and nitrogen, and an insulating film containing silicon and oxygen. The first charge storage film is included by two charge storage films.Type: ApplicationFiled: February 26, 2018Publication date: October 25, 2018Applicant: Renesas Electronics CorporationInventors: Masaru KADOSHIMA, Masao INOUE
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Patent number: 10062773Abstract: The present invention makes it possible, in a manufacturing process of a semiconductor device, to inhibit: impurities from diffusing from a substrate to a semiconductor layer; and the withstand voltage of a transistor from deteriorating. In the present invention, a first electrically conductive type epitaxial layer is formed over a first electrically conductive type base substrate. The impurity concentration of the epitaxial layer is lower than that of the base substrate. A second electrically conductive type first embedded layer and a second electrically conductive type second embedded layer are formed in the epitaxial layer. The second embedded layer is deeper than the first embedded layer, is kept away from the first embedded layer, and has an impurity concentration lower than the first embedded layer. A transistor is further formed in the epitaxial layer.Type: GrantFiled: May 14, 2015Date of Patent: August 28, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masaru Kadoshima, Masao Inoue
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Publication number: 20180061997Abstract: A memory cell includes a control gate electrode and a memory gate electrode. The control gate electrode is formed over the upper surface and the sidewall of a fin FA including apart of a semiconductor substrate. The memory gate electrode is formed over one side surface of the control gate electrode and the upper surface and the sidewall of the fin through an ONO film, in a position adjacent to the one side surface of the control gate electrode. Further, the control gate electrode and the memory gate electrode are formed of n-type polycrystalline silicon. A first metal film is provided between the gate electrode and the control gate electrode. A second metal film is provided between the ONO film and the memory gate electrode. A work function of the first metal film is greater than a work function of the second metal film.Type: ApplicationFiled: June 17, 2017Publication date: March 1, 2018Inventors: Yoshiyuki KAWASHIMA, Masao INOUE, Atsushi YOSHITOMI
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Patent number: 9725626Abstract: Provided is a hot-melt adhesive which satisfies both solidification rate and adhesiveness. A base polymer for a hot-melt adhesive which satisfies the following (1) and (2): (1) a modulus of elasticity in tension at 23° C. is 400 MPa or less; and (2) a semi-crystallization time at 23° C. is 20 minutes or less.Type: GrantFiled: May 27, 2014Date of Patent: August 8, 2017Assignee: IDEMITSU KOSAN CO., LTD.Inventors: Kazuhiro Hashima, Tomoaki Takebe, Yutaka Minami, Masao Inoue, Kenji Kobayashi
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Patent number: 9685565Abstract: The performance of a semiconductor device having a memory element is improved. An insulating film, which is a gate insulating film for a memory element, is formed on a semiconductor substrate, and a gate electrode for the memory element is formed on the insulating film. The insulating film has a first insulating film, a second insulating film thereon, and a third insulating film thereon. The second insulating film is a high-dielectric constant insulator film having a charge accumulating function and contains hafnium, silicon, and oxygen. Each of the first insulating film and the third insulating film has a band gap larger than the band gap of the second insulating film.Type: GrantFiled: August 27, 2014Date of Patent: June 20, 2017Assignee: Renesas Electronics CorporationInventors: Masaharu Mizutani, Masao Inoue, Hiroshi Umeda, Masaru Kadoshima
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Patent number: 9605185Abstract: A propylene-based polymer which satisfies the following (a1) to (d1): (a1) [mmmm]=60 to 80 mol %; (b1) weight-average molecular weight (Mw)=10,000 to 55,000; (c1) Mw/Mn?2.5; and (d1) [rmrm]?2.5 mol %.Type: GrantFiled: November 12, 2013Date of Patent: March 28, 2017Assignee: IDEMITSU KOSAN CO., LTD.Inventors: Kenji Kobayashi, Masao Inoue, Yutaka Minami
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Publication number: 20160380303Abstract: A nonaqueous electrolyte secondary battery includes a prismatic housing having an opening and a sealing member sealing the opening. The prismatic housing contains a flat-wound electrode assembly and a nonaqueous electrolyte. The flat-wound electrode assembly includes a positive electrode and a negative electrode. The positive electrode includes a positive electrode substrate and a positive electrode active material mixture layer formed on the positive electrode substrate. The positive electrode active material mixture layer contains lithium carbonate and lithium phosphate. The nonaqueous electrolyte contains lithium fluorosulfonate.Type: ApplicationFiled: June 22, 2016Publication date: December 29, 2016Applicant: SANYO Electric Co., Ltd.Inventors: Keisuke Minami, Yukari Kuratomi, Masao Inoue, Toyoki Fujihara, Naoya Nakanishi
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Patent number: 9514946Abstract: An improvement is achieved in the performance of a semiconductor device including a memory element. Over a semiconductor substrate, a gate electrode for the memory element is formed via an insulating film as a gate insulating film for the memory element. The insulating film includes first, second, third, fourth, and fifth insulating films in order of being apart from the substrate. The second insulating film has a charge storing function. The band gap of each of the first and third insulating films is larger than a band gap of the second insulating film. The band gap of the fourth insulating film is smaller than the band gap of the third insulating film. The band gap of the fifth insulating film is smaller than the band gap of the fourth insulating film.Type: GrantFiled: May 14, 2015Date of Patent: December 6, 2016Assignee: Renesas Electronics CorporationInventors: Masao Inoue, Yoshiki Maruyama, Tomoya Saito, Atsushi Yoshitomi
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Patent number: 9356110Abstract: To control a grain growth on laminated polysilicon films, a method of manufacturing a semiconductor device is provided. The method includes: forming a first polysilicon film (21) on a substrate (10); forming an interlayer oxide layer (22) on a surface of the first polysilicon film (21); forming a second polysilicon film (23) in contact with the interlayer oxide layer (22) above the first polysilicon film (21); and performing annealing at a temperature higher than a film formation temperature of the first and second polysilicon films in a gas atmosphere containing nitrogen, after formation of the second polysilicon film (23).Type: GrantFiled: February 5, 2014Date of Patent: May 31, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masao Inoue, Yoshiki Maruyama, Akio Nishida, Yorinobu Kunimune, Kota Funayama
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Publication number: 20160115360Abstract: Provided is a hot-melt adhesive which satisfies both solidification rate and adhesiveness. A base polymer for a hot-melt adhesive which satisfies the following (1) and (2): (1) a modulus of elasticity in tension at 23° C. is 400 MPa or less; and (2) a semi-crystallization time at 23° C. is 20 minutes or less.Type: ApplicationFiled: May 27, 2014Publication date: April 28, 2016Applicant: IDEMITSU KOSAN CO., LTD.Inventors: Kazuhiro HASHIMA, Tomoaki TAKEBE, Yutaka MINAMI, Masao INOUE, Kenji KOBAYASHI
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Publication number: 20150349143Abstract: An improvement is achieved in the performance of a semiconductor device including a memory element. Over a semiconductor substrate, a gate electrode for the memory element is formed via an insulating film as a gate insulating film for the memory element. The insulating film includes first, second, third, fourth, and fifth insulating films in order of being apart from the substrate. The second insulating film has a charge storing function. The band gap of each of the first and third insulating films is larger than a band gap of the second insulating film. The band gap of the fourth insulating film is smaller than the band gap of the third insulating film. The band gap of the fifth insulating film is smaller than the band gap of the fourth insulating film.Type: ApplicationFiled: May 14, 2015Publication date: December 3, 2015Inventors: Masao Inoue, Yoshiki Maruyama, Tomoya Saito, Atsushi Yoshitomi
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Publication number: 20150340479Abstract: The present invention makes it possible, in a manufacturing process of a semiconductor device, to inhibit: impurities from diffusing from a substrate to a semiconductor layer; and the withstand voltage of a transistor from deteriorating. In the present invention, a first electrically conductive type epitaxial layer is formed over a first electrically conductive type base substrate. The impurity concentration of the epitaxial layer is lower than that of the base substrate. A second electrically conductive type first embedded layer and a second electrically conductive type second embedded layer are formed in the epitaxial layer. The second embedded layer is deeper than the first embedded layer, is kept away from the first embedded layer, and has an impurity concentration lower than the first embedded layer. A transistor is further formed in the epitaxial layer.Type: ApplicationFiled: May 14, 2015Publication date: November 26, 2015Inventors: Masaru Kadoshima, Masao Inoue
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Publication number: 20150284600Abstract: A propylene-based polymer which satisfies the following (a1) to (d1): (a1) [mmmm]=60 to 80 mol %; (b1) weight-average molecular weight (Mw)=10,000 to 55,000; (c1) Mw/Mn?2.5; and (d1) [rmrm]?2.5 mol %.Type: ApplicationFiled: November 12, 2013Publication date: October 8, 2015Applicant: IDEMITSU KOSAN CO., LTD.Inventors: Kenji Kobayashi, Masao Inoue, Yutaka Minami
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Publication number: 20150060991Abstract: The performance of a semiconductor device having a memory element is improved. An insulating film, which is a gate insulating film for a memory element, is formed on a semiconductor substrate, and a gate electrode for the memory element is formed on the insulating film. The insulating film has a first insulating film, a second insulating film thereon, and a third insulating film thereon. The second insulating film is a high-dielectric constant insulator film having a charge accumulating function and contains hafnium, silicon, and oxygen. Each of the first insulating film and the third insulating film has a band gap larger than the band gap of the second insulating film.Type: ApplicationFiled: August 27, 2014Publication date: March 5, 2015Inventors: Masaharu Mizutani, Masao Inoue, Hiroshi Umeda, Masaru Kadoshima
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Publication number: 20140312406Abstract: To control a grain growth on laminated polysilicon films, a method of manufacturing a semiconductor device is provided. The method includes: forming a first polysilicon film (21) on a substrate (10); forming an interlayer oxide layer (22) on a surface of the first polysilicon film (21); forming a second polysilicon film (23) in contact with the interlayer oxide layer (22) above the first polysilicon film (21); and performing annealing at a temperature higher than a film formation temperature of the first and second polysilicon films in a gas atmosphere containing nitrogen, after formation of the second polysilicon film (23).Type: ApplicationFiled: February 5, 2014Publication date: October 23, 2014Applicant: Renesas Electronics CorporationInventors: Masao INOUE, Yoshiki MARUYAMA, Akio NISHIDA, Yorinobu KUNIMUNE, Kota FUNAYAMA
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Patent number: 8823110Abstract: Disclosed is a semiconductor device including a first MISFET of an n channel type and a second MISFET of a p channel type, each of the MISFETs being configured with a gate insulating film featuring a silicon oxide film or a silicon oxynitride film and a gate electrode including a conductive silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film in both the first and second MISFETs such that metal atoms with a surface density of 1×1013 to 5×1014 atoms/cm2 are contained near the interface and each of the first and second MISFETs having a channel region containing an impurity the concentration of which is equal to or lower than 1.2×1018/cm3.Type: GrantFiled: July 18, 2013Date of Patent: September 2, 2014Assignee: Renesas Electronics CorporationInventors: Yasuhiro Shimamoto, Jiro Yugami, Masao Inoue, Masaharu Mizutani