Patents by Inventor Masao Inoue

Masao Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7309747
    Abstract: A 1-butene polymer satisfying the following (1), (2) and either (3) or (3?): a process for producing the polymer; a resin modifier comprising the polymer; and a hot-melt adhesive containing the polymer. (1) The intrinsic viscosity [?] as measured in tetralin solvent at 135° C. is 0.01 to 0.5 dL/g. (2) The polymer is a crystalline resin having a melting point (Tm-D) of 0 to 100° C., the melting point being defined as the top of the peak observed on the highest-temperature side in a melting endothermic curve obtained with a differential scanning calorimeter (DSC) in a test in which a sample is held in a nitrogen atmosphere at ?10° C. for 5 min and then heated at a rate of 10° C./min. (3) The stereoregularity index {(mmmm)/(mmrr+rmmr)} is 30 or lower. (3?) The mesopentad content (mmmm) determined from a nuclear magnetic resonance (NMR) spectrum is 68 to 73%.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: December 18, 2007
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Yutaka Minami, Masami Kanamaru, Toyozo Fujioka, Tomoaki Takebe, Masao Inoue
  • Patent number: 7241995
    Abstract: There is disclosed an electron microscope equipped with a magnetic microprobe. The microscope can apply a strong electric field to a local area on a specimen made of a magnetic material. The magnetic flux density per unit area of the microprobe is high. The microscope includes a biprism for producing interference between an electron beam transmitted through the specimen and an electron beam passing through a vacuum. The specimen is held to a holder. The microprobe is made of a magnetic material and has a needle-like tip. The microscope further includes a moving mechanism capable of moving the microprobe toward and away from the specimen.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: July 10, 2007
    Assignees: Tohoku University, JEOL Ltd.
    Inventors: Daisuke Shindo, Yasukazu Murakami, Tetsuo Oikawa, Masao Inoue
  • Publication number: 20070138518
    Abstract: An active region on a semiconductor substrate is electrically isolated by trench isolation. A structure of the trench isolation is constituted of: a trench; a silicon oxide film formed on the inner wall of trench; an oxidation preventive film formed between silicon oxide film and semiconductor substrate; and a filling oxide film filling trench. Gate oxide film is formed by oxidation having a high capability by which radicals of at least one kind of hydrogen radicals and oxygen radicals are generated. Thereby, gate oxide film is formed so as to have a almost uniform thickness such that a thickness of a region directly above oxidation preventive film and a thickness of a region directly below gate electrode are almost the same is each other. According to the above procedure, there are obtained a semiconductor device having good transistor characteristics and a fabrication process therefor.
    Type: Application
    Filed: February 16, 2007
    Publication date: June 21, 2007
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Masao Inoue
  • Publication number: 20060273401
    Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.
    Type: Application
    Filed: April 24, 2006
    Publication date: December 7, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Shimpei Tsujikawa, Yasuhiko Akamatsu, Hiroshi Umeda, Jiro Yugami, Masaharu Mizutani, Masao Inoue, Junichi Tsuchimoto, Kouji Nomura
  • Publication number: 20060267116
    Abstract: An object of the present invention is to improve the performance of a semiconductor device having a CMISFET. Each of an n channel MISFET and a p channel MISFET which form the CMISFET includes a gate insulating film composed of a silicon oxynitride film and a gate electrode including a silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film with a surface density of 1×1013 to 5×1014 atoms/cm2. The impurity concentration of channel regions of the n channel MISFET and the p channel MISFET is controlled to be equal to or lower than 1.2×1018/cm3.
    Type: Application
    Filed: May 24, 2006
    Publication date: November 30, 2006
    Inventors: Yasuhiro Shimamoto, Jiro Yugami, Masao Inoue, Masaharu Mizutani
  • Publication number: 20060253651
    Abstract: The present invention provides a technique for, in the case in which a failure has occurred in a shared memory, controlling a period of a pseudo through operation to reduce a period in which performance of a disk array device falls. Control information is divided into management information, which is required to be duplexed, and directory information, which is only required to simplexed, and the management information and the directory information are stored in separate shared memories. In the case in which a failure has occurred in the shared memory of an expanded memory unit (Option) storing the directory information, the directory information is reestablished in the shared memory of a basic memory unit (Basic). The pseudo through operation is cancelled at the point when the directory information is reestablished. After a package of the expanded memory unit is replaced with a normal product, the directory information is reestablished again.
    Type: Application
    Filed: July 6, 2006
    Publication date: November 9, 2006
    Inventors: Masao Inoue, Katsuhiro Okumoto, Hisao Honma
  • Publication number: 20060214245
    Abstract: The semiconductor device includes a semiconductor substrate, a gate insulating film formed in contact with an upper side of the semiconductor substrate, and a gate electrode formed on the upper side of the gate insulating film and made of metal nitride or metal nitride silicide. A buffer layer for preventing diffusion of nitrogen and silicon is interposed between the gate insulating film and the gate electrode. Preferably, the buffer layer has a thickness of 5 nm or less. In the case where gate electrode contains Ti elements, and the gate insulating film contains Hf elements, the buffer layer preferably contains a titanium film.
    Type: Application
    Filed: March 9, 2006
    Publication date: September 28, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Jiro Yugami, Masao Inoue, Kenichi Mori, Shinsuke Sakashita
  • Publication number: 20060208325
    Abstract: A MISFET includes: a p type substrate having a channel region with an impurity concentration C; an insulating film made of SiO2 and formed on the channel region; and an insulating film made of HfSiON and formed on the gate insulating film. When there is a postulated MISFET including a postulated substrate having a channel region with the impurity concentration C and made of a material identical to the substrate and an insulating film made solely of SiON formed on the channel region, said impurity concentration C of channel region is set so that a maximum value of mobility of electrons in said channel region is higher than a maximum value of mobility of electrons in the postulated channel region. Thus, the power supply voltage can be reduced and the power consumption can be reduced.
    Type: Application
    Filed: March 13, 2006
    Publication date: September 21, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Masaharu Mizutani, Masao Inoue, Jiro Yugami, Junichi Tsuchimoto, Koji Nomura, Yasuhiro Shimamoto
  • Patent number: 7096317
    Abstract: The present invention provides a technique for, in the case in which a failure has occurred in a shared memory, controlling a period of a pseudo through operation to reduce a period in which performance of a disk array device falls. Control information is divided into management information, which is required to be duplexed, and directory information, which is only required to simplexed, and the management information and the directory information are stored in separate shared memories. In the case in which a failure has occurred in the shared memory of an expanded memory unit (Option) storing the directory information, the directory information is reestablished in the shared memory of a basic memory unit (Basic). The pseudo through operation is cancelled at the point when the directory information is reestablished. After a package of the expanded memory unit is replaced with a normal product, the directory information is reestablished again.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: August 22, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Masao Inoue, Katsuhiro Okumoto, Hisao Honma
  • Patent number: 7082568
    Abstract: An interactive data analysis support apparatus for supporting the analysis of data comprises: a cross tabulation display device for displaying according to specified summing up conditions a cross tabulation in which data to be analyzed is cross summed up, a cell specifying device for specifying at least one cell among a number of cells constituting the cross tabulation, and a graph display device for displaying the data to be analyzed as a graph within the range of the cell specified by the cell specifying device.
    Type: Grant
    Filed: January 27, 1998
    Date of Patent: July 25, 2006
    Assignee: Fujitsu Limited
    Inventors: Masaki Iwamoto, Masato Honda, Toshihiko Fushimi, Teruyuki Suzuki, Masao Inoue, Kouichi Tsuzuki, Hiromi Kato
  • Publication number: 20060054099
    Abstract: An aquarium-cleaning device, particularly an aquarium-cleaning device in which spent grain charcoal is used as formed charcoal. The formed charcoal provided by drying, forming, and carbonizing organic substances produced in food industries is used as a microorganism carrier. Such problems with a conventional device that the structure of the aquarium-cleaning device is complicated, the washing operation thereof is troublesome, and a filter medium must be frequently replaced can be solved by using the spent grain charcoal performing higher water-quality purification than a conventional activated charcoal as an aquarium-cleaning material.
    Type: Application
    Filed: November 28, 2003
    Publication date: March 16, 2006
    Applicant: ASAHI BREWERIES, LTD
    Inventors: Hiroyuki Okamoto, Toshio Sakai, Masao Inoue, Shuichi Yamasaki, Seiji Ishida, Satoshi Tsuneda, Akira Hirata
  • Publication number: 20060003532
    Abstract: An active region on a semiconductor substrate is electrically isolated by trench isolation. A structure of the trench isolation is constituted of: a trench; a silicon oxide film formed on the inner wall of trench; an oxidation preventive film formed between silicon oxide film and semiconductor substrate; and a filling oxide film filling trench. Gate oxide film is formed by oxidation having a high capability by which radicals of at least one kind of hydrogen radicals and oxygen radicals are generated. Thereby, gate oxide film is formed so as to have a almost uniform thickness such that a thickness of a region directly above oxidation preventive film and a thickness of a region directly below gate electrode are almost the same is each other. According to the above procedure, there are obtained a semiconductor device having good transistor characteristics and a fabrication process therefor.
    Type: Application
    Filed: September 9, 2005
    Publication date: January 5, 2006
    Applicant: Renesas Technology Corp.
    Inventor: Masao Inoue
  • Publication number: 20050274889
    Abstract: There is disclosed an electron microscope equipped with a magnetic microprobe. The microscope can apply a strong electric field to a local area on a specimen made of a magnetic material. The magnetic flux density per unit area of the microprobe is high. The microscope includes a biprism for producing interference between an electron beam transmitted through the specimen and an electron beam passing through a vacuum. The specimen is held to a holder. The microprobe is made of a magnetic material and has a needle-like tip. The microscope further includes a moving mechanism capable of moving the microprobe toward and away from the specimen.
    Type: Application
    Filed: May 20, 2005
    Publication date: December 15, 2005
    Applicants: Tohoku University, JEOL Ltd.
    Inventors: Daisuke Shindo, Yasukazu Murakami, Tetsuo Oikawa, Masao Inoue
  • Publication number: 20050260244
    Abstract: The particle obtained by spray-drying of a dispersion wherein a water-insoluble pesticidal active ingredient and oxidized polyethylene are dispersed in water can control release the water-insoluble pesticidal active ingredient.
    Type: Application
    Filed: October 29, 2004
    Publication date: November 24, 2005
    Inventors: Atsushi Watanabe, Masao Inoue
  • Patent number: 6964905
    Abstract: An active region on a semiconductor substrate is electrically isolated by trench isolation. A structure of the trench isolation is constituted of: a trench; a silicon oxide film formed on the inner wall of trench; an oxidation preventive film formed between silicon oxide film and semiconductor substrate; and a filling oxide film filling trench. Gate oxide film is formed by oxidation having a high capability by which radicals of at least one kind of hydrogen radicals and oxygen radicals are generated. Thereby, gate oxide film is formed so as to have a almost uniform thickness such that a thickness of a region directly above oxidation preventive film and a thickness of a region directly below gate electrode are almost the same is each other. According to the above procedure, there are obtained a semiconductor device having good transistor characteristics and a fabrication process therefor.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: November 15, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Masao Inoue
  • Publication number: 20050132136
    Abstract: The present invention provides a technique for, in the case in which a failure has occurred in a shared memory, controlling a period of a pseudo through operation to reduce a period in which performance of a disk array device falls. Control information is divided into management information, which is required to be duplexed, and directory information, which is only required to simplexed, and the management information and the directory information are stored in separate shared memories. In the case in which a failure has occurred in the shared memory of an expanded memory unit (Option) storing the directory information, the directory information is reestablished in the shared memory of a basic memory unit (Basic). The pseudo through operation is cancelled at the point when the directory information is reestablished. After a package of the expanded memory unit is replaced with a normal product, the directory information is reestablished again.
    Type: Application
    Filed: February 2, 2004
    Publication date: June 16, 2005
    Inventors: Masao Inoue, Katsuhiro Okumoto, Hisao Honma
  • Publication number: 20050119428
    Abstract: A 1-butene polymer satisfying the following (1), (2) and either (3) or (3?): a process for producing the polymer; a resin modifier comprising the polymer; and a hot-melt adhesive containing the polymer. (1) The intrinsic viscosity [?] as measured in tetralin solvent at 135° C. is 0.01 to 0.5 dL/g. (2) The polymer is a crystalline resin having a melting point (Tm-D) of 0 to 100° C., the melting point being defined as the top of the peak observed on the highest-temperature side in a melting endothermic curve obtained with a differential scanning calorimeter (DSC) in a test in which a sample is held in a nitrogen atmosphere at ?10° C. for 5 min and then heated at a rate of 10° C./min. (3) The stereoregularity index {(mmmm)/(mmrr+rmmr)} is 30 or lower. (3?) The mesopentad content (mmmm) determined from a nuclear magnetic resonance (NMR) spectrum is 68 to 73%.
    Type: Application
    Filed: February 19, 2003
    Publication date: June 2, 2005
    Inventors: Yutaka Minami, Masami Kanamaru, Toyozo Fujioka, Tomoaki Takebe, Masao Inoue
  • Publication number: 20050112167
    Abstract: The particle obtained by spray-drying of a dispersion wherein a water-insoluble pesticidal active ingredient and oxidized polyethylene are dispersed in water can control release the water-insoluble pesticidal active ingredient.
    Type: Application
    Filed: October 30, 2004
    Publication date: May 26, 2005
    Inventors: Atsushi Watanabe, Masao Inoue
  • Patent number: 6756156
    Abstract: In a rectangular alkaline storage battery, the sides of negative cores of negative electrode plates 10, which are disposed at the outermost positions of the group of electrode plates and oppose an outer casing can 40, are exposed. The pore ratios (ratio of total area taken up by pores to area of electrode plate) of the exposed cores must be made lower than those of the other unexposed cores. The pore ratio of the exposed negative core is specified as falling within a range of 10% to 40%. As a result, the negative electrode plates 10 are improved in binding strength, thereby inhibiting exfoliation of an active material. Further, there can be obtained a large rectangular alkaline storage battery which has superior permeability for a gas which would arise in the battery, an improved capacity ratio, and greater volumetric energy density.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: June 29, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasuhiko Ikeda, Masao Takee, Teruhiko Imoto, Masao Inoue, Tetsuyuki Murata, Atsutoshi Ako
  • Patent number: 6756647
    Abstract: A semiconductor device includes an n-type semiconductor substrate including a source region and a drain region in a main surface thereof, a high-permittivity insulator film including a high permittivity material and formed to cover an upper side of a region of the main surface of n-type semiconductor substrate, which region is interposed between source region and drain region. And the semiconductor device includes a boron-doped gate electrode formed above high-permittivity insulator film, and a high-permittivity nitride layer formed between high-permittivity insulator film and boron-doped gate electrode.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: June 29, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Masao Inoue, Akinobu Teramoto, Junichi Tsuchimoto