Abstract: Various methods are proposed for forming a gate insulation film, a metal gate layer, and others separately in an N-channel region and a P-channel region of an integrated circuit device having a CMIS or CMOS structure using a metal gate. One of the problems of the methods however has been that the process becomes complex. The present invention is that, in a manufacturing method of a CMOS integrated circuit device, a titanium-based nitride film for adjusting the electrical properties of a high-permittivity gate insulation film before a gate electrode film is formed includes a lower film containing a comparatively large quantity of titanium and an upper film containing a comparatively large quantity of nitrogen in an N-channel region and a P-channel region.

Abstract: Manufacturing technique for a semiconductor device having a first MISFET of an n channel-type and a second MISFET of a p channel type, including forming a first insulating film composed of a silicon oxide film or a silicon oxynitride film on a semiconductor substrate for forming a gate insulating film of the respective MISFETs; depositing metal elements on the first insulating film; forming of a silicon film on the first insulating film for the forming of a gate electrode of the respective MISFETs; and producing the respective gate electrodes by patterning the silicon film. The depositing of the metal films on the first insulating film is such that there is produced in the vicinity of the interface between the gate electrode and the gate insulating film a surface density of the metal elements within a range of 1×1013 to 5×1014 atoms/cm2.

Abstract: A semiconductor device including an n-channel-type MISFET (Qn) having an Hf-containing insulating film (5), which is a high dielectric constant gate insulating film containing hafnium, a rare-earth element, and oxygen as main components, and a gate electrode (GE1), which is a metal gate electrode, is manufactured. The Hf-containing insulating film (5) is formed by forming a first Hf-containing film containing hafnium and oxygen as main components, a rare-earth containing film containing a rare-earth element as a main component, and a second Hf-containing film containing hafnium and oxygen as main components sequentially from below and then causing these to react with one another.

Abstract: There is provided a technology capable of achieving, in a semiconductor device having a MISFET using an insulating film containing hafnium as a gate insulating film, an improvement in the reliability of a MISFET. In the present invention, the gate insulating film of an n-channel core transistor is provided with a structure different from that of the gate insulating film of a p-channel core transistor. Specifically, in the n-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfZrSiON film is used. On the other hand, in the p-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfSiON film is used.

Abstract: Various methods are proposed for forming a gate insulation film, a metal gate layer, and others separately in an N-channel region and a P-channel region of an integrated circuit device having a CMIS or CMOS structure using a metal gate. One of the problems of the methods however has been that the process becomes complex. The present invention is that, in a manufacturing method of a CMOS integrated circuit device, a titanium-based nitride film for adjusting the electrical properties of a high-permittivity gate insulation film before a gate electrode film is formed includes a lower film containing a comparatively large quantity of titanium and an upper film containing a comparatively large quantity of nitrogen in an N-channel region and a P-channel region.

Abstract: There are provided a semiconductor device in which the threshold voltage of a p-channel field effect transistor is reliably controlled to allow a desired characteristic to be obtained, and a manufacturing method thereof. As a heat treatment performed at a temperature of about 700 to 900° C. proceeds, in an element formation region, aluminum (Al) in an aluminum (Al) film is diffused into a hafnium oxynitride (HfON) film, and thereby added as an element to the hafnium oxynitride (HfON) film. In addition, aluminum (Al) and titanium (Ti) in a hard mask formed of a titanium aluminum nitride (TiAlN) film are diffused into the hafnium oxynitride (HfON) film, and thereby added as elements to the hafnium oxynitride (HfON) film.

Abstract: A 1-butene polymer satisfying the following (1), (2) and either (3) or (3?): a process for producing the polymer; a resin modifier comprising the polymer; and a hot-melt adhesive containing the polymer. (1) The intrinsic viscosity [?] as measured in tetralin solvent at 135° C. is 0.01 to 0.5 dL/g. (2) The polymer is a crystalline resin having a melting point (Tm-D) of 0 to 100° C., the melting point being defined as the top of the peak observed on the highest-temperature side in a melting endothermic curve obtained with a differential scanning calorimeter (DSC) in a test in which a sample is held in a nitrogen atmosphere at ?10° C. for 5 min and then heated at a rate of 10° C./min. (3) The stereoregularity index {(mmmm)/(mmrr+rmmr)} is 30 or lower. (3?) The mesopentad content (mmmm) determined from a nuclear magnetic resonance (NMR) spectrum is 68 to 73%.

Abstract: Manufacturing technique for a semiconductor device having a first MISFET of an n channel-type and a second MISFET of a p channel type, including forming a first insulating film composed of a silicon oxide film or a silicon oxynitride film on a semiconductor substrate for forming a gate insulating film of the respective MISFETs; depositing metal elements on the first insulating film; forming of a silicon film on the first insulating film for the forming of a gate electrode of the respective MISFETs; and producing the respective gate electrodes by patterning the silicon film. The depositing of the metal films on the first insulating film is such that there is produced in the vicinity of the interface between the gate electrode and the gate insulating film a surface density of the metal elements within a range of 1×1013 to 5×1014 atoms/cm2.

Abstract: An object of the present invention is to improve the performance of a semiconductor device having a CMISFET. Each of an n channel MISFET and a p channel MISFET which form the CMISFET includes a gate insulating film composed of a silicon oxynitride film and a gate electrode including a silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film with a surface density of 1×1013 to 5×1014 atoms/cm2. The impurity concentration of channel regions of the n channel MISFET and the p channel MISFET is controlled to be equal to or lower than 1.2×1018/cm3.

Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.

Abstract: The semiconductor device includes a semiconductor substrate, a gate insulating film formed in contact with an upper side of the semiconductor substrate, and a gate electrode formed on the upper side of the gate insulating film and made of metal nitride or metal nitride silicide. A buffer layer for preventing diffusion of nitrogen and silicon is interposed between the gate insulating film and the gate electrode. Preferably, the buffer layer has a thickness of 5 nm or less. In the case where gate electrode contains Ti elements, and the gate insulating film contains Hf elements, the buffer layer preferably contains a titanium film.

Abstract: An active region on a semiconductor substrate is electrically isolated by trench isolation. A structure of the trench isolation is constituted of a trench; a silicon oxide film formed on the inner wall of trench; an oxidation preventive film formed between silicon oxide film and semiconductor substrate; and a filling oxide film filling trench. Gate oxide film is formed by oxidation having a high capability by which radicals of at least one kind of hydrogen radicals and oxygen radicals are generated. Thereby, gate oxide film is formed so as to have a almost uniform thickness such that a thickness of a region directly above oxidation preventive film and a thickness of a region directly below gate electrode are almost the same is each other. According to the above procedure, there are obtained a semiconductor device having good transistor characteristics and a fabrication process therefor.

Abstract: To provide a double filtration blood purification apparatus that can be primed while generation of bubbles within each of a separating membrane in both of a blood component separator and a plasma component separator is avoided and also to provide a method of priming such blood purification apparatus. A cleansing liquid introducing passage 19 is provided, which is a passage dedicated to introduce a cleansing liquid P from a cleansing liquid supply source 57 into a plasma component separator 3 and, also, this cleansing liquid introducing passage 19 is provided with a dedicated, third pump 3. When the third and first pumps are driven in normal and reverse directions, respectively, by a controller 50, a sufficient pressure is applied to the cleansing liquid P by the third ump and the cleansing liquid P can be introduced into the plasma component separator 3.

Abstract: A blood processing apparatus in which whether or not circuit components are connected is ascertained, and a method of ascertaining a failure in such circuit connection is provided. By closing a blood return valve, disposed in a blood return passage for returning a blood, processed in a first blood processing unit, to patient's body, blocking a blood circuit including a blood introducing passage, the blood return passage and a delivery passage for delivering unnecessary blood component from the first blood processing unit, driving a first pump in the delivery passage in normal direction, and driving an air pump, fluidly connected with the blood introducing passage and the blood return passage, in reverse direction to discharge air from the circuit to generate negative pressure inside the circuit and the first blood processing unit, connection between the circuit and the first blood processing unit is ascertained.

Abstract: An active region on a semiconductor substrate is electrically isolated by trench isolation. A structure of the trench isolation is constituted of: a trench; a silicon oxide film formed on the inner wall of trench; an oxidation preventive film formed between silicon oxide film and semiconductor substrate; and a filling oxide film filling trench. Gate oxide film is formed by oxidation having a high capability by which radicals of at least one kind of hydrogen radicals and oxygen radicals are generated. Thereby, gate oxide film is formed so as to have a almost uniform thickness such that a thickness of a region directly above oxidation preventive film and a thickness of a region directly below gate electrode are almost the same is each other. According to the above procedure, there are obtained a semiconductor device having good transistor characteristics and a fabrication process therefor.

Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.

Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.

Abstract: The present invention provides a technique for, in the case in which a failure has occurred in a shared memory, controlling a period of a pseudo through operation to reduce a period in which performance of a disk array device falls. Control information is divided into management information, which is required to be duplexed, and directory information, which is only required to simplexed, and the management information and the directory information are stored in separate shared memories. In the case in which a failure has occurred in the shared memory of an expanded memory unit (Option) storing the directory information, the directory information is reestablished in the shared memory of a basic memory unit (Basic). The pseudo through operation is cancelled at the point when the directory information is reestablished. After a package of the expanded memory unit is replaced with a normal product, the directory information is reestablished again.

Abstract: A substrate to be processed by a patterning device has a group of a plurality of alignment marks formed within a predetermined area as an alignment area, each of the plurality of alignment marks being an information recording code that records its own location relative to a reference position on the substrate. In alignment of the substrate, an image of such an alignment area that includes a group of the plurality of alignment marks is captured. Thus, even if the area of image capturing is reduced with increasing image magnification, at least one of the plurality of alignment marks can be included in the image. One of the alignment marks whose images are included in this image is defined as a target mark, and the position of the substrate is derived based on the target mark in the image. Thus, the position of the substrate can be detected by a single image capturing operation.

Abstract: A 1-butene polymer satisfying the following (1), (2) and either (3) or (3?): a process for producing the polymer; a resin modifier comprising the polymer; and a hot-melt adhesive containing the polymer. (1) The intrinsic viscosity [?] as measured in tetralin solvent at 135° C. is 0.01 to 0.5 dL/g. (2) The polymer is a crystalline resin having a melting point (Tm-D) of 0 to 100° C., the melting point being defined as the top of the peak observed on the highest-temperature side in a melting endothermic curve obtained with a differential scanning calorimeter (DSC) in a test in which a sample is held in a nitrogen atmosphere at ?10° C. for 5 min and then heated at a rate of 10° C./min. (3) The stereoregularity index {(mmmm)/(mmrr+rmmr)} is 30 or lower. (3?) The mesopentad content (mmmm) determined from a nuclear magnetic resonance (NMR) spectrum is 68 to 73%.