Abstract: A resistance variable type synapse array apparatus that can perform STDP writing using a positive potential is provided. The synapse array apparatus includes a writing unit writing to a selected resistance variable type memory element in a crossbar array. The writing unit includes a driver generating a positive pulse signal corresponding to a positive part of a spike signal generated by a presynaptic neuron, a driver generating a positive pulse signal corresponding to a negative part of a spike signal generated by a postsynaptic neuron, a driver generating a positive pulse signal corresponding to a positive part of the spike signal generated by the postsynaptic neuron, and a driver generating a positive pulse signal corresponding to a negative part of the spike signal generated by the presynaptic neuron.

Abstract: A semiconductor memory device capable of reducing failure caused by a source side effect after a large number of W/E cycles is provided. A reading method of a NAND flash memory includes: dividing multiple word lines connected to each memory cell of a NAND string into a group 1 of word lines WL0 to WLi?1, a group 2 of word lines WLi to WLj, . . . , a group y of word lines WLj+1 to WLk?1, and a group x of word lines WLk to WLn, presetting a relationship that each readout voltage (Vread1, Vread2, . . . , Vready, and Vreadx) corresponding to each group increases toward a bit line side, and applying a readout voltage to a selected word line according to the relationship.

Abstract: An electron device using a crossbar array and capable of implementing a high-speed and high-reliability process is provided. An operational processing device (100) includes a crossbar array (110); a row selecting/driving circuit (120) electrically coupling to a row line; a column selecting/driving circuit (130) electrically coupling to a column line; and a control part (140) controlling each part. The control part (140) is capable of applying, from the row selecting/driving circuit (120), an output signal received by the row selecting/driving circuit (120) or applying, from the column selecting/driving circuit (130), an output signal received by the column selecting/driving circuit (130).

Abstract: A semiconductor device is provided. The semiconductor device includes a unique-information generation portion, a detection portion, a memory portion, and a readout portion. The unique-information generation portion operates in a plurality of operation environments to generate unique information. The unique information includes stable information and unstable information. The stable information is constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments. The detection portion detects the unstable information. The memory portion stores the unique information and identification information for identifying the unstable information. The readout portion reads out the unique information and the identification information and outputs the unique information and the identification information to an external portion.

Abstract: A semiconductor device is provided. The semiconductor device includes a unique-information generation portion, a detection portion, a memory portion, and a readout portion. The unique-information generation portion operates in a plurality of operation environments to generate unique information. The unique information includes stable information and unstable information. The stable information is constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments. The detection portion detects the unstable information. The memory portion stores the unique information and identification information for identifying the unstable information. The readout portion reads out the unique information and the identification information and outputs the unique information and the identification information to an external portion.

Abstract: Provide a resistive random-access memory device having an optimized 3D construction. A resistive random-access memory includes a plurality of pillars, a plurality of bit lines, and a memory cell. The pillars extend vertically along the main surface of the substrate. The bit lines extend in a horizontal direction. The memory cell is formed at the intersection of the pillars and the bit lines. The memory cell includes a gate insulating film, a semiconductor film, and a resistive element. The gate insulating film is formed on the circumference of the pillar. The semiconductor film is formed on the circumference of gate insulating film and provides a channel area. The resistive element is formed on the circumference of the semiconductor film. A first electrode area on the circumference of the resistive element and a second electrode area facing the first electrode area are electrically connected to a pair of adjacent bit lines.

Abstract: Provided is a resistive random-access memory device, including: multiple pillars, extending in a vertical direction with respect to a main surface of a substrate; multiple bit lines, extending in a horizontal direction with respect to the main surface of the substrate; and a memory cell, formed at an intersection of the pillars and the bit lines. The memory cell includes a gate insulating film formed on an outer periphery of the pillars, a semiconductor film formed on an outer periphery of the gate insulating film and providing a channel region, and a variable resistance element formed on a part of an outer periphery of the semiconductor film. An electrode region of an outer periphery of the variable resistance element is connected to one of a pair of adjacent bit lines, and the semiconductor film is connected to the other of the pair of adjacent bit lines.

Abstract: An electron device using a crossbar array and capable of implementing a high-speed and high-reliability process is provided. An operational processing device (100) includes a crossbar array (110); a row selecting/driving circuit (120) electrically coupling to a row line; a column selecting/driving circuit (130) electrically coupling to a column line; and a control part (140) controlling each part. The control part (140) is capable of applying, from the row selecting/driving circuit (120), an output signal received by the row selecting/driving circuit (120) or applying, from the column selecting/driving circuit (130), an output signal received by the column selecting/driving circuit (130).

Abstract: A memory circuit and a semiconductor device are provided. The memory circuit has a function of recovering data when power is suddenly shutdown. The memory device includes a bi-stable circuit capable of holding complementary data respectively at nodes N1 and N2; a first non-volatile memory circuit, connected to the node; and a second non-volatile memory circuit connected to the node. The first non-volatile memory circuit stores boot data, and the second non-volatile memory circuit inverts a logic level of the data held at the second node when the second non-volatile memory circuit stores data at the second node.

Abstract: An NOR flash memory comprising a memory cell of a 3D structure and a manufacturing method thereof are provided. The flash memory 100 includes a plurality of columnar portions 120, a plurality of charge accumulating portions 130 and a plurality of control gates 140. The columnar portions 120 extend from a surface of a silicon substrate 110 in a vertical direction and include an active region. The charge accumulating portions 130 are formed by way of surrounding a side portion of each columnar portion 120. The control gates 140 are formed by way of surrounding a side portion of each charge accumulating portion 130. One end portion of the columnar portion 120 is electrically connected to a bit line 150 via a contact hole, and another end portion of the columnar portion 120 is electrically connected to a conductive region formed on a surface of the silicon substrate 110.

Abstract: An NOR flash memory comprising a memory cell of a 3D structure and a manufacturing method thereof are provided. The flash memory 100 includes a plurality of columnar portions 120, a plurality of charge accumulating portions 130 and a plurality of control gates 140. The columnar portions 120 extend from a surface of a silicon substrate 110 in a vertical direction and include an active region. The charge accumulating portions 130 are formed by way of surrounding a side portion of each columnar portion 120. The control gates 140 are formed by way of surrounding a side portion of each charge accumulating portion 130. One end portion of the columnar portion 120 is electrically connected to a bit line 150 via a contact hole, and another end portion of the columnar portion 120 is electrically connected to a conductive region formed on a surface of the silicon substrate 110.

Abstract: A memory circuit and a semiconductor device are provided. The memory circuit has a function of recovering data when power is suddenly shutdown. The memory device includes a bi-stable circuit capable of holding complementary data respectively at nodes N1 and N2; a first non-volatile memory circuit, connected to the node; and a second non-volatile memory circuit connected to the node. The first non-volatile memory circuit stores boot data, and the second non-volatile memory circuit inverts a logic level of the data held at the second node when the second non-volatile memory circuit stores data at the second node.

Abstract: A semiconductor device is provided. The semiconductor device includes a unique-information generation portion, a detection portion, a memory portion, and a readout portion. The unique-information generation portion operates in a plurality of operation environments to generate unique information. The unique information includes stable information and unstable information. The stable information is constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments. The detection portion detects the unstable information. The memory portion stores the unique information and identification information for identifying the unstable information. The readout portion reads out the unique information and the identification information and outputs the unique information and the identification information to an external portion.

Abstract: A semiconductor device is provided. The semiconductor device includes a unique-information generation portion, a detection portion, a memory portion, and a readout portion. The unique-information generation portion operates in a plurality of operation environments to generate unique information. The unique information includes stable information and unstable information. The stable information is constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments. The detection portion detects the unstable information. The memory portion stores the unique information and identification information for identifying the unstable information. The readout portion reads out the unique information and the identification information and outputs the unique information and the identification information to an external portion.

Abstract: A semiconductor device preventing reduction of reliability due to the impact of heat after shipment is provided. A semiconductor device of the disclosure includes a built-in self-test circuit 110 and a resistive random-access memory. The built-in self-test circuit 110 includes a reforming information setting part 230 for performing reforming of the resistive random-access memory. When the operation of a forming execution part 220 or a test execution part 210 is performed, a flag is set to “1” for the reforming information setting part 230. Moreover, when a power supply mounted on a circuit board by IR reflow is turned on, the built-in self-test control part 200 references the flag of the reforming information setting part 230, and if the flag is “1”, then the forming execution part 220 executes the reforming of the resistive random-access memory.

Abstract: A semiconductor device is provided. The semiconductor device includes a unique-information generation portion, a detection portion, a memory portion, and a readout portion. The unique-information generation portion operates in a plurality of operation environments to generate unique information. The unique information includes stable information and unstable information. The stable information is constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments. The detection portion detects the unstable information. The memory portion stores the unique information and identification information for identifying the unstable information. The readout portion reads out the unique information and the identification information and outputs the unique information and the identification information to an external portion.

Abstract: A semiconductor memory device for suppressing a decrease of durability caused by erasure of a block unit or programming of a word unit is provided. A resistance change memory 100 includes a memory array 110 and a controller 120. The memory array 110 stores data by a reversible and nonvolatile variable resistance element. When erasing a selected block of the memory array 110 in response to an external erasure command, the controller 120 sets an EF flag indicating the selected block is in an erasure state without changing block data. The controller 120 further includes a reading unit. The reading unit outputs data of a selected word or data indicating the erasure based on the EF flag when reading the selected word of the memory array 110 in response to an external reading command.

Abstract: A semiconductor device with improved generation function of unique information is provided. The semiconductor device includes an integrated circuit designed or fabricated based on a general design condition or manufacturing condition, an input/output circuit, and a unique-information generation circuit to generate unique information of the semiconductor device. The unique-information generation circuit includes a circuit for PUF and a code-generation unit. The circuit for PUF is fabricated based on the design condition or manufacturing condition which is different from the general design condition or manufacturing condition and has a factor which makes variations of circuit components become large. The code-generation unit generates codes based on the output of the circuit for PUF.

Abstract: A NOR flash memory comprising a memory cell having a three-dimensional structure for saving power consumption is provided. The flash memory of the present invention includes a pillar part, a charge accumulating part, an insulating part, a control gate and a selecting gate. The pillar part extends in a vertical direction from a surface of a substrate and includes a conductive semiconductor material. The charge accumulating part is formed by surrounding the pillar part. The insulating part is formed by surrounding the pillar part. The control gate is formed by surrounding the charge accumulating part. The selecting gate is formed by surrounding the insulating part. One end of the pillar part is electrically connected to a bit line via a contact hole and another one end of the pillar part is electrically connected to a conductive region formed on the surface of the substrate.

Abstract: A semiconductor memory device for suppressing a decrease of durability caused by erasure of a block unit or programming of a word unit is provided. A resistance change memory 100 includes a memory array 110 and a controller 120. The memory array 110 stores data by a reversible and nonvolatile variable resistance element. When erasing a selected block of the memory array 110 in response to an external erasure command, the controller 120 sets an EF flag indicating the selected block is in an erasure state without changing block data. The controller 120 further includes a reading unit. The reading unit outputs data of a selected word or data indicating the erasure based on the EF flag when reading the selected word of the memory array 110 in response to an external reading command.