Abstract: The invention provides a NAND-type semiconductor memory device capable of high speed operation. A semiconductor memory device of the invention includes: a memory array, which forms a plurality of memory cells arranged in a matrix direction; a vertical selecting mechanism, which couples to the memory array, and selects the memory cells in a vertical direction of the memory array according to a vertical address signal; a horizontal selecting mechanism, which couples to the memory array, and selects the memory cells in a horizontal direction of the memory array according to a horizontal address signal; and a controlling mechanism, which reads data from the memory cells or writes data into the memory cells. A plurality of cell units is disposed in the memory array. Each cell unit is consisted of a data memory cell which storages data and a reference memory cell which storages reference data.

Abstract: A semiconductor memory device is provided, which can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).

Abstract: A semiconductor storage device restraining the variation in threshold voltage of a memory unit is provided. The steps of the programming method for a flash memory include: setting a bit line to a program voltage or a program-protection voltage; applying a program pulse to the selected page; and verifying the programming of the selected page. Also, the steps further include: when the verification result indicates that there is a failed-shift memory cell which was passed previously but is failed presently, setting the voltage of the bit line of the failed shift memory to a mitigation voltage for mitigating the voltage of the next program pulse.

Abstract: A flash memory with low power consumption and rapid operations is disclosed, including a memory array of memory cells, a word line selection circuit for selecting a row of cells, a current-type sensing circuit electrically connected with each bit line for sensing the current of a selected bit line, and an erase unit erasing the cells in a selected block of the array. The erase unit includes: an erase sequence that determines whether the current of each bit line in the erased block is larger than a first value and ends the erasure if the result is “yes”, and a soft-program sequence that performs a soft program verification, which applies a soft-program voltage to all word lines in the erased block and determines whether the current of each bit line is lower than a second value, and ends the soft programming if the result is “yes”.

Abstract: A flash memory capable of writing or deleting a split block is provided. A flash memory includes a memory array comprising a plurality of blocks, and a word line selection circuit, wherein each of the plurality of blocks is formed by a plurality of cell units in a well. The cell unit comprises N memory cells, a selection transistor coupled to one terminal of the memory cells, a selection transistor coupled to the other terminal of the memory cells, and a dummy selection transistor coupled between the memory cells. The word line selection circuit splits the block into a first block and a second block to use according to the operation of data writing or data deleting.

Abstract: The invention provides a voltage regulator. The voltage regulator (100) of the invention includes a comparison circuit (20) and a voltage divider circuit (110). The voltage divider circuit (110) has a PMOS transistor (T6) connected to a voltage source (VDD) and resistors (R1, R2, R3, R4, R5 and R6) serially connected between the transistor (T6) and a reference voltage. A feedback voltage generated from a node (N3) between resistors R4 and R5 is provided to the comparison circuit (20). In addition, a middle voltage (Vm) generated from a node (Nc) of the resistors is provided to a well region, so the parasitic capacitance is reduced.

Abstract: A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.

Abstract: A non-volatile semiconductor memory includes a memory array. In a programming operation, programming pulses are applied to a page of the memory array to program data to the page. In an erase operation, erase pulses are applied to a block of the memory array to erase data in the block. The non-volatile semiconductor memory performs a pre-program operation before the erase operation and a post-erase operation after the erase operation. In the pre-program operation, each page of the block is programmed according to voltage information relating programming pulses. In the erase operation, data in the block is erased according to the voltage information relating programming pulses.

Abstract: A semiconductor storage device restraining the variation in threshold voltage of a memory unit is provided. The steps of the programming method for a flash memory include: setting a bit line to a program voltage or a program-protection voltage; applying a program pulse to the selected page; and verifying the programming of the selected page. Also, the steps further include: when the verification result indicates that there is a failed-shift memory cell which was passed previously but is failed presently, setting the voltage of the bit line of the failed shift memory to a mitigation voltage for mitigating the voltage of the next program pulse.

Abstract: The invention provides a NAND-type semiconductor memory device capable of high speed operation. A semiconductor memory device of the invention includes: a memory array, which forms a plurality of memory cells arranged in a matrix direction; a vertical selecting mechanism, which couples to the memory array, and selects the memory cells in a vertical direction of the memory array according to a vertical address signal; a horizontal selecting mechanism, which couples to the memory array, and selects the memory cells in a horizontal direction of the memory array according to a horizontal address signal; and a controlling mechanism, which reads data from the memory cells or writes data into the memory cells. A plurality of cell units is disposed in the memory array. Each cell unit is consisted of a data memory cell which storages data and a reference memory cell which storages reference data.

Abstract: A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.

Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

Abstract: A flash memory with low power consumption and rapid operations is disclosed, including a memory array of memory cells, a word line selection circuit for selecting a row of cells, a current-type sensing circuit electrically connected with each bit line for sensing the current of a selected bit line, and an erase unit erasing the cells in a selected block of the array. The erase unit includes: an erase sequence that determines whether the current of each bit line in the erased block is larger than a first value and ends the erasure if the result is “yes”, and a soft-program sequence that performs a soft program verification, which applies a soft-program voltage to all word lines in the erased block and determines whether the current of each bit line is lower than a second value, and ends the soft programming if the result is “yes”.

Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

Abstract: An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. One embodiment of the invention also provides a method of controlling the semiconductor device.

Abstract: A semiconductor memory device, having a memory array which has two memory banks which can be accessed simultaneously is provided. A word line selection circuit selects the word line according to the row address information, and a controller controls the word line selection circuit according to the received instruction. The controller performs the first read operation of the word line selection circuit in response to a first read command, and performs the second read operation of the word line selection circuit in response to a second read command. The first read operation selects the n-th word line of one of the memory banks and selects the (n+1)-th or (n?1)-th word line of the other memory bank, and the second read operation selects the n-th word line of one of the memory banks and selects the n-th word line of the other memory bank.

Abstract: A non-volatile semiconductor memory device, comprising: a non-volatile memory array, storing multi-values by setting a plurality of different threshold voltages for each memory cell, and a control circuit, controlling a write-in operation to the memory cell array. When data have been written into the memory cell, the control circuit selects an adjacent word line, uses an erasing level to perform write-in which is weaker than the data write-in, and verifies soft programming of the amount of one page, such that a narrow-banded erasing level distribution is realized in an adjacent memory cell.

Abstract: A flash memory 100 capable of reducing electric fields applied to the word lines on a memory array and reducing a chip area, includes a memory array 110, a word line decoder 120 disposed at an end of the memory array on the row direction, selecting a predetermined memory block in the memory array according to an address signal, and outputting a selecting signal to the selected memory block, and a word line drive circuit 130 comprising a switch circuit arranged between the memory arrays 110A and 110B and switching the application of the work voltage to a memory cell according to the selecting signal, and a pump circuit raising the voltage level of the selecting signal. The word line decoder 120 has lines WR(i) to transmit the selecting signals. The lines WR(i) are connected to the switch circuit of the word line drive circuit 130.

Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.

Abstract: A non-volatile semiconductor memory includes a memory array. In a programming operation, programming pulses are applied to a page of the memory array to program data to the page. In an erase operation, erase pulses are applied to a block of the memory array to erase data in the block. The non-volatile semiconductor memory performs a pre-program operation before the erase operation and a post-erase operation after the erase operation. In the pre-program operation, each page of the block is programmed according to voltage information relating programming pulses. In the erase operation, data in the block is erased according to the voltage information relating programming pulses.