Patents by Inventor Masaru Yano
Masaru Yano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8693249Abstract: A semiconductor memory device includes a memory array, a row selection circuit and a bit line selection circuit. The memory array is composed of a plurality of cell units, wherein each cell unit has memory cells connected in series. The row selection circuit selects the memory cells in a row direction of the cell units, and the bit line selection circuit selects a bit line from an even bit line and an odd bit line coupled to the cell units. The bit line selection circuit includes a first selection part including selection transistors for selectively coupling the even or odd bit line to a sensor circuit and a second selection part including bias transistors for selectively coupling the even or odd bit line to a voltage source providing biases, wherein the bias transistors and the memory cells are formed in a common well.Type: GrantFiled: January 13, 2012Date of Patent: April 8, 2014Assignee: Winbond Electronics Corp.Inventors: Masaru Yano, Lu-Ping Chiang
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Publication number: 20140063970Abstract: A semiconductor memory device performing high speed reading with a miniaturized sensing circuit is provided. A pre-charge voltage from a virtual potential VPRE? is provided to an odd bit line when an even bit line is selected, the pre-charge voltage is provided from a source voltage supply unit 230 to a shared odd source line SL_o, a ground potential is provided from the source voltage supply unit 230 to an even source line SL_e.Type: ApplicationFiled: May 27, 2013Publication date: March 6, 2014Applicant: Winbond Electronics Corp.Inventors: Masaru Yano, Lu-Ping Chiang
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Patent number: 8659950Abstract: A semiconductor memory device performing high speed reading with a miniaturized sensing circuit is provided. A pre-charge voltage from a virtual potential VPRE? is provided to an odd bit line when an even bit line is selected, the pre-charge voltage is provided from a source voltage supply unit 230 to a shared odd source line SL_o, a ground potential is provided from the source voltage supply unit 230 to an even source line SL_e.Type: GrantFiled: May 27, 2013Date of Patent: February 25, 2014Assignee: Winbond Electronics Corp.Inventors: Masaru Yano, Lu-Ping Chiang
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Patent number: 8611167Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.Type: GrantFiled: September 11, 2012Date of Patent: December 17, 2013Assignee: Spansion LLCInventors: Akira Ogawa, Masaru Yano
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Publication number: 20130155774Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.Type: ApplicationFiled: September 11, 2012Publication date: June 20, 2013Inventors: Akira OGAWA, Masaru YANO
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Publication number: 20130145093Abstract: A non-volatile semiconductor memory is provided, including a memory array having a first and a second memory planes, a page buffer, holding data transmitted by pages selected by address information from a memory array; data register, capable of serially outputting data received by the page buffer according to a clock signal. The pages selected by the first and the second memory planes are simultaneously transmitted to the page buffer. The data reading includes: transmitting the data of the second page of the second memory plane from the page buffer to the data register when the data of the first page of the first memory plane is outputted from the data register; transmitting the data of the second page of the first memory plane from the page buffer to the data register when the data of the second page of the second memory plane is outputted from the data register.Type: ApplicationFiled: July 19, 2012Publication date: June 6, 2013Applicant: WINBOND ELECTRONICS CORP.Inventors: Takehiro Kaminaga, Masaru Yano
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Publication number: 20130077413Abstract: A flash memory 100 capable of reducing electric fields applied to the word lines on a memory array and reducing a chip area, includes a memory array 110, a word line decoder 120 disposed at an end of the memory array on the row direction, selecting a predetermined memory block in the memory array according to an address signal, and outputting a selecting signal to the selected memory block, and a word line drive circuit 130 comprising a switch circuit arranged between the memory arrays 110A and 110B and switching the application of the work voltage to a memory cell according to the selecting signal, and a pump circuit raising the voltage level of the selecting signal. The word line decoder 120 has lines WR(i) to transmit the selecting signals. The lines WR(i) are connected to the switch circuit of the word line drive circuit 130.Type: ApplicationFiled: February 24, 2012Publication date: March 28, 2013Inventor: Masaru YANO
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Publication number: 20130064016Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.Type: ApplicationFiled: March 6, 2012Publication date: March 14, 2013Inventors: Akira OGAWA, Masaru YANO
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Publication number: 20130016560Abstract: A semiconductor memory device includes a memory array, a row selection circuit and a bit line selection circuit. The memory array is composed of a plurality of cell units, wherein each cell unit has memory cells connected in series. The row selection circuit selects the memory cells in a row direction of the cell units, and the bit line selection circuit selects a bit line from an even bit line and an odd bit line coupled to the cell units. The bit line selection circuit includes a first selection part including selection transistors for selectively coupling the even or odd bit line to a sensor circuit and a second selection part including bias transistors for selectively coupling the even or odd bit line to a voltage source providing biases, wherein the bias transistors and the memory cells are formed in a common well.Type: ApplicationFiled: January 13, 2012Publication date: January 17, 2013Inventors: Masaru YANO, Lu-Ping CHIANG
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Patent number: 8351268Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.Type: GrantFiled: October 5, 2011Date of Patent: January 8, 2013Assignee: Spansion LLCInventors: Akira Ogawa, Masaru Yano
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Patent number: 8325523Abstract: An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. One embodiment of the invention also provides a method of controlling the semiconductor device.Type: GrantFiled: August 1, 2011Date of Patent: December 4, 2012Assignee: Spansion LLCInventors: Masaru Yano, Kazuhide Kurosaki, Mototada Sakashita
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Publication number: 20120230106Abstract: A semiconductor memory device, having a memory array which has two memory banks which can be accessed simultaneously is provided. A word line selection circuit selects the word line according to the row address information, and a controller controls the word line selection circuit according to the received instruction. The controller performs the first read operation of the word line selection circuit in response to a first read command, and performs the second read operation of the word line selection circuit in response to a second read command. The first read operation selects the n-th word line of one of the memory banks and selects the (n+1)-th or (n?1)-th word line of the other memory bank, and the second read operation selects the n-th word line of one of the memory banks and selects the n-th word line of the other memory bank.Type: ApplicationFiled: November 15, 2011Publication date: September 13, 2012Inventor: Masaru YANO
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Patent number: 8264901Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.Type: GrantFiled: October 11, 2010Date of Patent: September 11, 2012Assignee: Spansion LLCInventors: Akira Ogawa, Masaru Yano
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Publication number: 20120084491Abstract: A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.Type: ApplicationFiled: September 30, 2011Publication date: April 5, 2012Inventors: Eungjoon Park, Robin John Jigour, Jooweon Park, Masaru Yano
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Publication number: 20120069676Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.Type: ApplicationFiled: October 5, 2011Publication date: March 22, 2012Inventors: Akira OGAWA, Masaru YANO
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Patent number: 8130584Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.Type: GrantFiled: October 15, 2010Date of Patent: March 6, 2012Assignee: Spansion LLCInventors: Akira Ogawa, Masaru Yano
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Publication number: 20110286273Abstract: An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. One embodiment of the invention also provides a method of controlling the semiconductor device.Type: ApplicationFiled: August 1, 2011Publication date: November 24, 2011Inventors: Masaru YANO, Kazuhide KUROSAKI, Mototada SAKASHITA
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Patent number: 8045388Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.Type: GrantFiled: June 18, 2010Date of Patent: October 25, 2011Assignee: Spansion LLCInventors: Akira Ogawa, Masaru Yano
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Patent number: 8018767Abstract: The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. The present invention also provides a method of controlling the semiconductor device.Type: GrantFiled: November 20, 2008Date of Patent: September 13, 2011Assignee: Spansion, LLCInventors: Masaru Yano, Kazuhide Kurosaki, Mototada Sakashita
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Publication number: 20110182116Abstract: The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit (16) connected to a core cell (12) provided in a nonvolatile memory cell array (10), a second current-voltage conversion circuit (26) connected to a reference cell (22) through a reference cell data line (24), a sense amplifier (18) sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit (28) comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit (30) charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened.Type: ApplicationFiled: October 11, 2010Publication date: July 28, 2011Inventors: Akira OGAWA, Masaru YANO