Abstract: An NOR flash memory comprising a memory cell of a 3D structure and a manufacturing method thereof are provided. The flash memory 100 includes a plurality of columnar portions 120, a plurality of charge accumulating portions 130 and a plurality of control gates 140. The columnar portions 120 extend from a surface of a silicon substrate 110 in a vertical direction and include an active region. The charge accumulating portions 130 are formed by way of surrounding a side portion of each columnar portion 120. The control gates 140 are formed by way of surrounding a side portion of each charge accumulating portion 130. One end portion of the columnar portion 120 is electrically connected to a bit line 150 via a contact hole, and another end portion of the columnar portion 120 is electrically connected to a conductive region formed on a surface of the silicon substrate 110.

Abstract: A NADN flash memory and a program method thereof suppressing an influence caused by FG coupling and having a high reliability are provided. The program method of the flash memory of the present invention includes a step of selecting pages of a memory array, a step of applying a programming voltage to even-numbered pages of the selected pages, a step of soft-programming odd-numbered pages of the selected pages and a step of applying the programming voltage to the odd-numbered pages after the programming of the even-numbered pages is completed.

Abstract: A semiconductor device preventing reduction of reliability due to the impact of heat after shipment is provided. A semiconductor device of the disclosure includes a built-in self-test circuit 110 and a resistive random-access memory. The built-in self-test circuit 110 includes a reforming information setting part 230 for performing reforming of the resistive random-access memory. When the operation of a forming execution part 220 or a test execution part 210 is performed, a flag is set to “1” for the reforming information setting part 230. Moreover, when a power supply mounted on a circuit board by IR reflow is turned on, the built-in self-test control part 200 references the flag of the reforming information setting part 230, and if the flag is “1”, then the forming execution part 220 executes the reforming of the resistive random-access memory.

Abstract: A manufacturing method of a semiconductor memory device is provided. The semiconductor memory device can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).

Abstract: A semiconductor device is provided. The semiconductor device includes a unique-information generation portion, a detection portion, a memory portion, and a readout portion. The unique-information generation portion operates in a plurality of operation environments to generate unique information. The unique information includes stable information and unstable information. The stable information is constant in the plurality of operation environments, and the unstable information is different in at least two of the plurality of operation environments. The detection portion detects the unstable information. The memory portion stores the unique information and identification information for identifying the unstable information. The readout portion reads out the unique information and the identification information and outputs the unique information and the identification information to an external portion.

Abstract: A semiconductor device with improved generation function of unique information is provided. The semiconductor device includes an integrated circuit designed or fabricated based on a general design condition or manufacturing condition, an input/output circuit, and a unique-information generation circuit to generate unique information of the semiconductor device. The unique-information generation circuit includes a circuit for PUF and a code-generation unit. The circuit for PUF is fabricated based on the design condition or manufacturing condition which is different from the general design condition or manufacturing condition and has a factor which makes variations of circuit components become large. The code-generation unit generates codes based on the output of the circuit for PUF.

Abstract: A manufacturing method of a semiconductor memory device is provided. The semiconductor memory device can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).

Abstract: Provided is an erase method for a non-volatile semiconductor memory device to compensate for the change in property of a memory cell, in proportion to the number of data rewrites to the memory cell. The erase method has an erase step to erase charges of a charge accumulation layer by applying an erase voltage to a channel region of a selected memory cell, and a soft-programming step to perform soft-programming to the charges in the accumulation layer by virtue of applying a soft-programming voltage which is smaller than a programming voltage to program the memory cell. The erase voltage is increased step by step when it is applied repeatedly. The soft-programming voltage is decreased step by step when it is applied repeatedly.

Abstract: A manufacturing method of a semiconductor memory device is provided. The semiconductor memory device can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).

Abstract: A non-volatile semiconductor memory device having an improved layout structure to achieve low power consumption, high speed and miniaturization is provided. A flash memory of the present invention includes a memory array formed with NAND type strings. The memory array includes a plurality of global blocks, one global block includes a plurality of blocks, and one block includes a plurality of NAND type strings. A plurality of local bit lines are shared by each of the plurality of blocks in one global block, a plurality of global bit lines are shared by the plurality of global blocks, and a connecting element selectively connecting one global bit line to n local bit lines is included. When a read-out operation and program operation are executed, one global bit line is shared by n local bit lines.

Abstract: A NADN flash memory and a program method thereof suppressing an influence caused by FG coupling and having a high reliability are provided. The program method of the flash memory of the present invention includes a step of selecting pages of a memory array, a step of applying a programming voltage to even-numbered pages of the selected pages, a step of soft-programming odd-numbered pages of the selected pages and a step of applying the programming voltage to the odd-numbered pages after the programming of the even-numbered pages is completed.

Abstract: A non-volatile semiconductor memory device having an improved layout structure to achieve low power consumption, high speed and miniaturization is provided. A flash memory of the present invention includes a memory array formed with NAND type strings. The memory array includes a plurality of global blocks, one global block includes a plurality of blocks, and one block includes a plurality of NAND type strings. A plurality of local bit lines are shared by each of the plurality of blocks in one global block, a plurality of global bit lines are shared by the plurality of global blocks, and a connecting element selectively connecting one global bit line to n local bit lines is included. When a read-out operation and program operation are executed, one global bit line is shared by n local bit lines.

Abstract: A method for repairing of the invention includes steps as follows: storing redundant information including an address of the bad column, identification information for identifying a failure in which one of an even column or an odd column of the bad column and an address of a redundant column of a redundant memory region for repairing the bad column; determining whether a column address of a selected column is consistent with the address of the bad column based on the redundant information; when consistent, converting a column of the bad column having the failure into a column of the redundant column based on the identification information; and not converting another column of the bad column without the failure into another column of the redundant column.

Abstract: Provided is an erase method for a non-volatile semiconductor memory device to compensate for the change in property of a memory cell, in proportion to the number of data rewrites to the memory cell. The erase method has an erase step to erase charges of a charge accumulation layer by applying an erase voltage to a channel region of a selected memory cell, and a soft-programming step to perform soft-programming to the charges in the accumulation layer by virtue of applying a soft-programming voltage which is smaller than a programming voltage to program the memory cell. The erase voltage is increased step by step when it is applied repeatedly. The soft-programming voltage is decreased step by step when it is applied repeatedly.

Abstract: A method for repairing of the invention includes steps as follows: storing redundant information including an address of the bad column, identification information for identifying a failure in which one of an even column or an odd column of the bad column and an address of a redundant column of a redundant memory region for repairing the bad column; determining whether a column address of a selected column is consistent with the address of the bad column based on the redundant information; when consistent, converting a column of the bad column having the failure into a column of the redundant column based on the identification information; and not converting another column of the bad column without the failure into another column of the redundant column.

Abstract: A manufacturing method of a semiconductor memory device is provided. The semiconductor memory device can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).

Abstract: The invention provides a programming method for a NAND-type flash memory capable of reducing the drop in reliability due to data-rewriting. The programming method includes: when a block program mode is executed to perform programming for a plurality of pages in a block, while the data to be programmed is being loaded into a cache memory; and erasing the selected block; and programming the data to be programmed which is loaded into the cache memory to the erased block.

Abstract: A semiconductor memory device is provided, which can suppress current leakage generated during a programming action so that the programming action can be executed with high reliability. A flash memory of this invention has a memory array in which NAND type strings are formed. Gates of memory cells in row direction of strings are commonly connected to a word line. Gates of bit line select transistors are commonly connected to a select gate line (SGD). Gates of source line select transistors are commonly connected to a select gate line (SGS). An interval (S4) of the select gate line (SGS) and a gate of a word line (WL0) adjacent to the select gate line (SGS) is larger than an interval (S1) of the select gate line (SGD) and a gate of a word line (WL7) adjacent to the select gate line (SGD).

Abstract: The invention provides a programming method for a NAND-type flash memory capable of reducing the drop in reliability due to data-rewriting. The programming method includes: when a block program mode is executed to perform programming for a plurality of pages in a block, while the data to be programmed is being loaded into a cache memory; and erasing the selected block; and programming the data to be programmed which is loaded into the cache memory to the erased block.

Abstract: The invention provides a voltage regulator. The voltage regulator (100) of the invention includes a comparison circuit (20) and a voltage divider circuit (110). The voltage divider circuit (110) has a PMOS transistor (T6) connected to a voltage source (VDD) and resistors (R1, R2, R3, R4, R5 and R6) serially connected between the transistor (T6) and a reference voltage. A feedback voltage generated from a node (N3) between resistors R4 and R5 is provided to the comparison circuit (20). In addition, a middle voltage (Vm) generated from a node (Nc) of the resistors is provided to a well region, so the parasitic capacitance is reduced.