Abstract: The present invention is a memory circuit, comprises: a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells disposed in the positions of intersection between the bit lines and the word lines; and a page buffer, which is connected to the bit line and which detects memory cell data by judging with predetermined sense timing the potential of the bit line when a pre-charged bit line potential is discharged in accordance to a cell current of a selected memory cell. Further the sense timing differs in accordance with the position of the selected memory cell in the memory cell array.

Abstract: The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates.

Abstract: Techniques, including a system and method, for reducing the total time for writing a plurality of pages to a NAND-type flash memory array are provided. In one embodiment, the writing is divided into two parts. The first part receives and holds the next page in an intermediate buffer, while the present page, stored in the page buffer, is used to program the memory array. Then the next page is loaded into the page buffer. In parallel with the next page being programmed into the memory array, another page is input and held in the intermediate buffer. Thus, substantially gapless writing of the plurality of pages to the NAND-type flash memory array is achieved with the associated reduction in total time.

Abstract: A nonvolatile semiconductor memory with a plurality of banks in which copy back is performed between banks. An input circuit accepts input of a copy back command which requests a data transfer in the memory. When the copy back command is input from the input circuit, a judgment circuit judges whether a source and a destination are in the same bank. If the judgment circuit judges that the source and the destination are in the same bank, a first transfer circuit transfers data in the same bank. If the judgment circuit judges that the source and the destination are in different banks, a second transfer circuit transfers data between the two different banks.

Abstract: A nonvolatile semiconductor memory device includes a memory core circuit which is nonvolatile and stores multi-values therein by setting different thresholds to memory cells, and a control circuit which controls data writing into the memory core circuit, wherein the control circuit programs first memory cells to be at one of the thresholds by setting the one of the thresholds not only to the first memory cells but also to second memory cells that are subsequently to be programmed to any one of the thresholds higher than the one of the thresholds, the control circuit successively performing programming in an ascending order of the thresholds.

Abstract: A method is provided for selecting a group of memory blocks in a flash memory device given their starting and ending addresses. The method compares the two addresses to determine the multi-block first bit location which is the most significant bit location where the starting and ending addresses have different bits. The method then generates a converted memory block address where bits more significant than the multi-block first bit location are the ending address bits and where bits less significant than, or equal in significance to, the multi-block first bit location are equal to a logic 1. The method also generates a converted complementary memory block address identical to the other converted address except that bits in the bit locations more significant than the multi-block first bit location are the complements of the ending address bits.

Abstract: System for programming verification that intelligently reprograms failed bits without excessively stressing bit logic in the device. The system operates to detect bits that have failed a programming verify operation and to reprogram these bits with an adjusted programming voltage so as to obtain the desired Vt while reducing stress on the bits and achieving a narrow Vt distribution.

Abstract: System for programming verification that intelligently reprograms failed bits without excessively stressing bit logic in the device. The system operates to detect bits that have failed a programming verify operation and to reprogram these bits with an adjusted programming voltage so as to obtain the desired Vt while reducing stress on the bits and achieving a narrow Vt distribution.

Abstract: Techniques, including a system and method, for reducing the total time for writing a plurality of pages to a NAND-type flash memory array are provided. In one embodiment, the writing is divided into two parts. The first part receives and holds the next page in an intermediate buffer, while the present page, stored in the page buffer, is used to program the memory array. Then the next page is loaded into the page buffer. In parallel with the next page being programmed into the memory array, another page is input and held in the intermediate buffer. Thus, substantially gapless writing of the plurality of pages to the NAND-type flash memory array is achieved with the associated reduction in total time.

Abstract: When data is programmed into nonvolatile memory cells, a programming voltage is applied, with increasing, to the memory cells a plurality of times. During this data programming, the increment of the programming voltage is set to a first voltage, which is maintained until the threshold voltages of all the memory cells to be programmed reach an initial value. Thereafter, the increment is set to a second voltage, which is maintained until the threshold voltages reach a target value. Increasing the programming voltage without varying the increment thereof allows the threshold voltages of the memory cells to approach the target value in a smaller number of times programmed. Additionally, setting the increment of the programming voltage to the second voltage after the threshold voltages exceed the initial value can minimize the deviation of the threshold voltages from the target value. Consequently, the programming time of the memory cells can be reduced.

Abstract: The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates. Processes for making the memory device according to the invention are also disclosed.

Abstract: Flash memory array systems and methods are disclosed for producing a supply regulated boost voltage, wherein the application of a supply voltage to a supply voltage level detection circuit (e.g., analog to digital converter, digital thermometer) which is used to generating one or more supply voltage level detection signals from measurement of the supply voltage level applied to the voltage boost circuit, which may be used as a boosted wordline voltage for the read mode operations of programmed memory cells, and wherein the supply voltage level detection signals are applied to a boosted voltage compensation circuit to generate one or more boosted voltage compensation signals which are applied to a voltage boost circuit operable to generate a regulated boosted voltage for a flash memory array of programmed core cells.

Abstract: Flash memory array systems and methods are disclosed for producing a supply regulated boost voltage, wherein the application of a supply voltage to a supply voltage level detection circuit (e.g., analog to digital converter, digital thermometer) which is used to generating one or more supply voltage level detection signals from measurement of the supply voltage level applied to the voltage boost circuit, which may be used as a boosted wordline voltage for the read mode operations of programmed memory cells, and wherein the supply voltage level detection signals are applied to a boosted voltage compensation circuit to generate one or more boosted voltage compensation signals which are applied to a voltage boost circuit operable to generate a regulated boosted voltage for a flash memory array of programmed core cells.

Abstract: Disclosed are output drivers for integrated circuit chips which receive a second supply voltage VCCQ for driving signals off the chips. The output drivers according to the present invention can accept a wide range of voltage values for the second supply voltage VCCQ, and control their rise and fall slew times so that there is only a small variation in the slew times over a wide range of VCCQ values. The charging and discharging of the driver's pull-up and pull-down transistors is varied as a function of the second supply voltage VCCQ. In one set of embodiments, constructive discharge current branches and charging current branches are selectively activated depending upon the value of VCCQ. In other embodiments, counteracting discharge current branches and charging current branches are selectively activated depending upon the value of VCCQ.

Abstract: A NAND type flash memory device has a reference bit line and a reference page buffer to control sensing time during program and erase verification operations. Each reference memory cell in the reference bit line is pre-programmed with a reference bit. A set initiation signal triggers detection and latching of the reference bit by the reference page buffer. When the reference bit is latched, an output of the reference page buffer is used as a set signal to trigger the program and erase verification operations of corresponding memory cells.

Abstract: A non-volatile memory device includes a plurality of MOS transistors 34 and 36 connected to respective word lines 16 and 18 to allow individual pages of memory stored in the memory cells 8a, 10a and 8b, 10b on the respective word lines 16 and 18 to be erased and erase verified. A method of erasing a page of memory cells includes the steps of applying an erase voltage to one of the MOS transistors 16 and 18 to erase the page of memory cells along the respective word line, and applying an initial erase-inhibit floating voltage to other MOS transistors which are connected to the word lines unselected for page erase. In an erase verify mode, an erase verify voltage is applied to the word line which was selected for page erase in the erase mode, and an erase verify unselect voltage is applied to the word lines which was not selected for page erase.

Abstract: In the programming of a non-volatile memory device, such as a NAND flash memory device 100, a positive bias voltage V.sub.bias is applied to a bit line 44 to set a respective memory gate 44a in a programmed state. In a further embodiment, the positive bias voltage V.sub.bias is obtained by dividing the select drain gate voltage V.sub.cc using two resistors 56 and 58 connected in series.

Abstract: The shift register includes a front stage latch portion for inputting input data when a clock signal is at a first level and latching the input data when the clock signal is at a second level, a rear stage latch portion for inputting data from the front stage latch portion when the clock signal is at the second level and latching the input data when the clock signal is at the first level, an input switch for connecting a data input terminal to the front stage latch portion when a mode switching signal is at a first level, and a feedback switch for connecting the rear stage latch portion to the front stage latch portion when the mode switching signal is at a second level. A latch mode clock signal is provided as the aforementioned clock signal when the mode switching signal is at the first level, and a counter mode clock signal or front stage shift register latch output signal is provided as the aforementioned clock signal when the mode switching signal is at the second level.

Abstract: Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply.

Abstract: Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply.