Patents by Inventor Masashi Hashimoto

Masashi Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Synchronous DRAM with control data buffer
    Patent number: 6738860
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: May 18, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Synchronous data system with control data buffer
    Patent number: 6735667
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: May 11, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Process of using a DRAM with address control data
    Patent number: 6735668
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: May 11, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Process for controlling reading data from a DRAM array
    Patent number: 6732225
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: May 4, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • System with control data buffer for transferring streams of data
    Patent number: 6732224
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: May 4, 2004
    Assignee: Texas Instrument Incorporated
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Memory device for transferring streams of data
    Patent number: 6732226
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: May 4, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Synchronous DRAM system with control data
    Patent number: 6728829
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: April 27, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Synchronous data transfer system
    Patent number: 6728828
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of the addresses is the random access address stored in the address buffer register (36).
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: April 27, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Synchronous DRAM System with control data
    Patent number: 6662291
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Grant
    Filed: July 5, 2002
    Date of Patent: December 9, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • System with control data buffer for transferring streams of data
    Publication number: 20030208669
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Application
    Filed: May 30, 2003
    Publication date: November 6, 2003
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Traffic quality measurement apparatus and method
    Publication number: 20030202471
    Abstract: A measurement apparatus for measuring traffic of packets with high time resolution is provided. The measurement apparatus includes an accumulation part for accumulating packet lengths of packets having predetermined header information in successively received packets, and storing an accumulated value of the packet lengths in a storage; and a periodic reading part for reading the accumulated value from the storage at predetermined time intervals, and outputting the accumulated value.
    Type: Application
    Filed: April 29, 2003
    Publication date: October 30, 2003
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Takahiro Murooka, Masashi Hashimoto, Toshiaki Miyazaki
  • Synchronous DRAM with control data buffer
    Publication number: 20030200381
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Application
    Filed: May 30, 2003
    Publication date: October 23, 2003
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Synchronous dram system with control data
    Publication number: 20030200416
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Application
    Filed: May 30, 2003
    Publication date: October 23, 2003
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Synchronous data transfer system
    Publication number: 20030200415
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of the addresses is the random access address stored in the address buffer register (36).
    Type: Application
    Filed: May 23, 2003
    Publication date: October 23, 2003
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Process for controlling reading data from a DRAM array
    Publication number: 20030200417
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Application
    Filed: June 2, 2003
    Publication date: October 23, 2003
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • RAM with fewer address terminals than data terminals
    Publication number: 20030196067
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Application
    Filed: June 2, 2003
    Publication date: October 16, 2003
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Process of operating a DRAM system
    Publication number: 20030196070
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Application
    Filed: June 2, 2003
    Publication date: October 16, 2003
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Synchronous data system with control data buffer
    Publication number: 20030196034
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Application
    Filed: May 30, 2003
    Publication date: October 16, 2003
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Memory device for transferring streams of data
    Publication number: 20030196068
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Application
    Filed: June 2, 2003
    Publication date: October 16, 2003
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
  • Process of using a dram with address control data
    Publication number: 20030196069
    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
    Type: Application
    Filed: June 2, 2003
    Publication date: October 16, 2003
    Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait