Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asychronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: A method for laser-assisted separation and enrichment of silicon isotopes such as 28Si, 29Si and 30Si on the basis of infrared multiple-photon dissociation of silicon halides represented by Si2F6, wherein the silicon halides are irradiated synchronously with multiple infrared pulsed laser beams at different wavelengths.

Abstract: A control circuit generates a right-turn or left-turn signal from a direction indicator lamp based on a direction indicating signal from a turn signal switch in a scooter as a vehicle. The control circuit then calculates a turning angle of the scooter from an angular speed V of the scooter detected by an angular speed sensor, and cancels the turn signal generated from the direction indicator lamp on the condition that the turning angle be equal to or greater than a reference turning angle, that a vehicle speed N detected by a vehicle speed sensor be equal to or higher than a reference vehicle speed, and that the angular speed detected by the angular speed sensor be equal to or lower than a reference angular speed.

Abstract: A gated field effect transistor (gated-FET) in which the body of the FET is electrically isolated from the substrate thereby reducing leakage current through parasitic bipolar action. The back-bias of the channel of the FET is jointly controlled by a diode coupled with a capacitor.

Abstract: The present invention has for its object to provide a novel catalyst by use of which methylbenzenes can be oxidized in gaseous phase in the presence of molecular oxygen to give the corresponding aromatic aldehydes in high yields, a process for producing an aromatic aldehyde from the corresponding methylbenzene in a high yield by use of said catalyst, and a process for producing cyclohexanedimethanol which comprises hydrogenating phthalaldehyde among the aromatic aldehydes which can be obtained as above.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: To efficiently access pixel data stored in memory in the X direction and Y direction when carrying out error correction processing. In a data output section 10, a pixel block consisting the desired 2×2 pixel data W1-W4 is selected by inputting a address, and pixel data continuously aligned in an arbitrary direction, that is, in the X direction or Y direction, are output inputting output pixel selection signals V1 and V2. Specifically, two pixels W1, W2, or W3, W4, which are continuously aligned in the X direction, are selected when signals V1 and V2=0 and V1=0 and V2=1, and two arbitrary pixels W1, W3 or W2, W4, which are continuously aligned in the Y direction, are selected when signal V1=1 and V2=0 and V1 and V2=1.

Abstract: A control circuit generates a right turn or left-turn signal from a direction indicator lamp based on a direction indicating signal from a turn signal switch in a scooter as a vehicle. The control circuit then calculates a turning angle of the scooter from an angular speed V of the scooter detected by an angular speed sensor, and cancels the turn signal generated from the direction indicator lamp on the condition that the turning angle be equal to or greater than a reference turning angle, that a vehicle speed N detected by a vehicle speed sensor be equal to or higher than a reference vehicle speed, and that the angular speed detected by the angular speed sensor be equal to or lower than a reference angular speed.

Abstract: A gated field effect transistor (gated-FET) in which the body of the FET is electrically isolated from the substrate thereby reducing leakage current through parasitic bipolar action. The back-bias of the channel of the FET is jointly controlled by a diode coupled with a capacitor.

Abstract: A circuit for measuring the access time of a memory circuit. The circuit includes a storage element 908 having an input terminal, an output terminal, and a clock terminal. The input terminal of the storage element is coupled to an output of the memory circuit 900. A clock signal source 906 is coupled to the clock terminal of the storage element and to a clock terminal of the memory circuit. The circuit also includes test circuitry 902 coupled to address and control terminals of the memory circuit and to the output terminal of the storage element. The test circuitry is operable to store or generate a test data pattern and compare the pattern to data output from the storage element. In one embodiment, the storage element is a data latch comprising a clock-enabled inverter serially coupled with a flip-flop. The flip-flop in one embodiment is a cross-coupled inverter storage cell or “keeper”.

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract: The objective of the invention is to conduct access of image data in the diagonal direction at high-speed by using the page mode.The memory region is divided into four memory arrays (15.sub.-1 to 15.sub.-4), and shifters (13.sub.-1 to 13.sub.-4) [sic: (14.sub.-1 to 14.sub.-4)] are provided that can shift the page address by one address in relation to each memory array. The image data are divided into sub-blocks of 4.times.4, 4 data items for the vertical correction are stored in the same memory array, and the page addresses for the sub-blocks connected in the horizontal direction are stored so as to be consecutive. In the case of accessing the data in the diagonal direction, when the data straddle adjacent blocks 4 at a time from the top, the page address is shifted by a shifter for the memory array containing that straddled column.

Abstract: A semiconductor memory device having a redundancy scheme is disclosed. A memory cell array includes a number of standard word lines sets and at least one redundant word line set. Each standard word line within a standard word line set is selected by lower address signals, and couples memory cells to a different combination of bit line than the other standard word lines within the standard word line set. In a standard mode of operation, transfer gates coupled to each bit line are enabled according to the lower address signals. Each redundant word line within a redundant word line set is selected by a defective address, and couples memory cells to a different combination of bit lines than the other redundant word lines within the redundant word line set. In a redundant mode of operation, the transfer gates are enabled according to an activated redundant word line to ensure that the proper combination of bit lines is coupled to sense amplifier circuits.

Abstract: In the design of an integrated circuit for comparing serial data signals, the number of transistor elements can be reduced by implementing the comparison gate (12) based on the associated truth table rather than by using a general comparison gate component. Using this method, an exclusive OR gate (22) can be implemented using two transistor elements (221, 222), an exclusive NOR gate (52) can be implemented using two transistor elements (521, 522), an AND gate (62) can be implemented using a single transistor element (621), and an OR gate (72) can be implemented using a single transistor element (721). The reduced number of elements used to implement the comparison gates can provide a transistor element saving in the associated circuit.

Abstract: In a dynamic random access memory unit 10, a circuit, 61.sub.0 -61.sub.N.sbsb.--.sub.1, 615, and 617, is provided in which a non-change of each address signal of an address signal group during a next consecutive clock cycle blocks the application of the read activation control signal to the memory unit 10. In this manner, the memory unit 10 is inactive (i.e., does not perform a read operation) during the modify portion of a read-modify-write operation so that potential conflicts in the operation of the memory unit 10 are avoided.

Abstract: A memory unit 30 is provided with a first and second sense amplifier array 32A and 32B. The storage cells 31 of the memory unit are coupled to both sense amplifier arrays. A control unit 34 is provided which controls the operation of the two sense amplifier arrays. The control unit determines through which sense amplifier array data signals are transferred to and from the storage cells. The sense amplifier array not exchanging signals with the I/O terminals can perform the precharge operations and write-back operations. Synchronous operation of the memory unit and a data processing unit can be maintained by alternating the sense amplifier array performing the current memory access operation.

Abstract: Method and device for enabling high-speed write/read operation of image information in units of blocks, so as to fully meet the demand on high-speed operation of MPEG, etc. Eight memory arrays MA1-MA8 are parallelly-connected in image memory unit 10; hence, in each memory array MAi, image can be written/read individually under control of write address generating circuit 12, memory array control logic 14, and read address generating circuit 16. The input/output terminals of memory arrays MA1-MA8 are connected to half-pel operation circuit 24 through eight data registers DREG1-DREG8 of input/output buffer 18, eight row selectors YSEL1-YSEL8 and column selector XSEL of selector circuit 20, and data bus 22.