Patents by Inventor Masayuki Kitamura

Masayuki Kitamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9991159
    Abstract: According to some embodiments, a semiconductor device manufacturing method includes forming a sacrificial film on a material film. The method includes processing the sacrificial film, and forming a first groove in the sacrificial film having a first width and a second groove in the sacrificial film having a second width larger than the first width, the material film defining a base of the first groove and a base of the second groove. The method includes forming a catalyst layer on the sacrificial film, and on the base of the first groove and the base of the second groove. The method includes forming a first metal film having a thickness equal to or larger than half the first width and smaller than half the second width on the catalyst layer by plating. The method includes removing at least a portion of the first metal film in the second groove while leaving a portion of the first metal film in the first groove unremoved.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: June 5, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Fuyuma Ito, Yasuhito Yoshimizu, Yuya Akeboshi, Hisashi Okuchi, Masayuki Kitamura
  • Publication number: 20180090438
    Abstract: According to some embodiments, a semiconductor device includes a substrate and an insulating film that is provided on the substrate. The device further includes a contact plug which includes a barrier metal layer provided in the insulating film, and a plug material layer provided in the insulating film, the barrier metal layer disposed between the plug material layer and the insulating film. The barrier metal layer includes at least a first layer including a first metal element and nitrogen, and a second layer including a second metal element different from the first metal element, and nitrogen.
    Type: Application
    Filed: March 3, 2017
    Publication date: March 29, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Masayuki KITAMURA, Atsuko SAKATA
  • Publication number: 20180082893
    Abstract: According to some embodiments, a semiconductor device manufacturing method includes forming a sacrificial film on a material film. The method includes processing the sacrificial film, and forming a first groove in the sacrificial film having a first width and a second groove in the sacrificial film having a second width larger than the first width, the material film defining a base of the first groove and a base of the second groove. The method includes forming a catalyst layer on the sacrificial film, and on the base of the first groove and the base of the second groove. The method includes forming a first metal film having a thickness equal to or larger than half the first width and smaller than half the second width on the catalyst layer by plating. The method includes removing at least a portion of the first metal film in the second groove while leaving a portion of the first metal film in the first groove unremoved.
    Type: Application
    Filed: March 3, 2017
    Publication date: March 22, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Fuyuma ITO, Yasuhito YOSHIMIZU, Yuya AKEBOSHI, Hisashi OKUCHI, Masayuki KITAMURA
  • Patent number: 9911753
    Abstract: According to one embodiment, an insulating layer is provided above a stairstep portion of a stacked body. A first cover film is provided between the stairstep portion and the insulating layer. The first cover film is of a material different from the insulating layer. A separation portion divides the stacked body and the insulating layer. A second cover film is provided at a side surface of the insulating layer on the separation portion side. The second cover film is of a material different from the insulating layer.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: March 6, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Masayuki Kitamura, Atsuko Sakata, Satoshi Wakatsuki, Takeshi Ishizaki, Daisuke Ikeno, Tomotaka Ariga
  • Patent number: 9905462
    Abstract: According to one embodiment, the stacked body includes a plurality of metal films, a plurality of silicon oxide films, and a plurality of intermediate films. The intermediate films are provided between the metal films and the silicon oxide films. The intermediate films contain silicon nitride. Nitrogen composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the metal films than on sides of interfaces between the intermediate films and the silicon oxide films. Silicon composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the silicon oxide films than on sides of interfaces between the intermediate films and the metal films.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: February 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Atsuko Sakata, Takeshi Ishizaki, Shinya Okuda, Kei Watanabe, Masayuki Kitamura, Satoshi Wakatsuki, Daisuke Ikeno, Junichi Wada, Hirotaka Ogihara
  • Publication number: 20170345644
    Abstract: There is provided a method of forming a carbon film on a workpiece, which includes: loading the workpiece into a process chamber; supplying a gas containing a boron-containing gas into the process chamber to form a seed layer composed of a boron-based thin film on a surface of the workpiece; and subsequently, supplying a hydrocarbon-based carbon source gas and a pyrolysis temperature lowering gas containing a halogen element and which lowers a pyrolysis temperature of the hydrocarbon-based carbon source gas into the process chamber, heating the hydrocarbon-based carbon source gas to a temperature lower than the pyrolysis temperature to pyrolyze the hydrocarbon-based carbon source gas, and forming the carbon film on the workpiece by a thermal CVD.
    Type: Application
    Filed: May 22, 2017
    Publication date: November 30, 2017
    Inventors: Akira SHIMIZU, Masayuki KITAMURA, Yosuke WATANABE
  • Publication number: 20170342548
    Abstract: There is provided a method of forming a carbon film on a workpiece, which includes: loading the workpiece into a process chamber, and supplying a hydrocarbon-based carbon source gas and a pyrolysis temperature drop gas for dropping a pyrolysis temperature of the hydrocarbon-based carbon source gas into the process chamber, pyrolyzing the hydrocarbon-based carbon source gas by heating the hydrocarbon-based carbon source gas at a temperature lower than a pyrolysis temperature of the hydrocarbon-based carbon source gas, and forming the carbon film on the workpiece by a thermal CVD method. An iodine-containing gas is used as the pyrolysis temperature drop gas.
    Type: Application
    Filed: May 19, 2017
    Publication date: November 30, 2017
    Inventors: Akira SHIMIZU, Masayuki KITAMURA, Yosuke WATANABE, Akinobu KAKIMOTO
  • Publication number: 20170316973
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Inventors: Masayuki KITAMURA, Atsuko SAKATA, Makoto WADA, Yuichi YAMAZAKI, Masayuki KATAGIRI, Akihiro KAJITA, Tadashi SAKAI, Naoshi SAKUMA, Ichiro MIZUSHIMA
  • Patent number: 9779978
    Abstract: A method of manufacturing a semiconductor device uses a semiconductor manufacturing apparatus including a turn table allowing placement of at least first and second semiconductor substrates and being capable of moving positions of the first and the second semiconductor substrates by turning, a first film forming chamber, and a second film forming chamber. The first and the second film forming chambers are provided with an opening capable of loading and unloading the first and the second semiconductor substrates by lifting and lowering the first and the second semiconductor substrates placed on the turn table. The method includes transferring the first and the second semiconductor substrates between the first and the second film forming chambers by turning the turn fable and lifting and lowering the first and the second semiconductor substrates placed on the turn table; and forming a stack of films above the first and the second semiconductor substrates.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 3, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Kei Watanabe, Junichi Wada, Masayuki Kitamura, Takeshi Ishizaki, Shinya Okuda, Hirotaka Ogihara, Satoshi Wakatsuki, Daisuke Ikeno
  • Patent number: 9780111
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a film having semi-conductivity or conductivity, and a memory film. The stacked body includes a plurality of metal layers, a plurality of insulating layers, and a plurality of intermediate layers stacked on a major surface of the substrate. The film extends in the stacked body in a stacking direction of the stacked body. The memory film is provided between the film and the metal layers. The metal layers are tungsten layers and the intermediate layers are tungsten nitride layers. Or the metal layers are molybdenum layers and the intermediate layers are molybdenum nitride layers.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: October 3, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Takeshi Ishizaki, Junichi Wada, Atsuko Sakata, Kei Watanabe, Masayuki Kitamura, Daisuke Ikeno, Satoshi Wakatsuki, Hirotaka Ogihara, Shinya Okuda
  • Patent number: 9761531
    Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes interconnects each including a catalyst layer and a graphene layer thereon. The catalyst layer includes a first to fifth catalyst regions arranged along a first direction in order of the first to fifth catalyst regions. The first, third and fifth catalyst regions include upper surfaces higher than those of the second and fourth catalyst regions. Adjacent ones of the first to fifth catalyst regions are in contact with each other. A distance between the first and the third catalyst region and a distance between the third and fifth catalyst region are greater than a mean free path of graphene. The graphene layer includes a first graphene layer on the second catalyst region and a second graphene layer on the fourth catalyst region.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: September 12, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuro Saito, Masayuki Kitamura, Atsuko Sakata, Makoto Wada, Akihiro Kajita, Tadashi Sakai
  • Patent number: 9754793
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched, the mask layer containing tungsten and boron, a composition ratio of the tungsten being not less than 30%, patterning the mask layer, and performing a dry etching to the layer to be etched using the mask layer being patterned, and forming a hole or a slit in the layer to be etched.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 5, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Nakao, Shunsuke Ochiai, Yusuke Oshiki, Kei Watanabe, Mitsuhiro Omura, Kosuke Horibe, Atsuko Sakata, Junichi Wada, Soichi Yamazaki, Masayuki Kitamura, Yuya Matsubara
  • Publication number: 20170229301
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.
    Type: Application
    Filed: September 18, 2012
    Publication date: August 10, 2017
    Inventors: Masayuki KITAMURA, Atsuko SAKATA, Makoto WADA, Yuichi YAMAZAKI, Masayuki KATAGIRI, Akihiro KAJITA, Tadashi SAKAI, Naoshi SAKUMA, Ichiro MIZUSHIMA
  • Patent number: 9728473
    Abstract: A method of manufacturing a semiconductor device includes forming a film along a surface of a semiconductor substrate in a first surface area state having a first surface area by supplying a reaction gas at a first flow rate. The method further includes detecting a transition from the first surface area state to a second surface area state having a second surface area different from the first surface area. The method still further includes forming the film by changing the flow rate of the reaction gas from the first flow rate to a second flow rate different from the first flow rate after detecting the transition from the first surface area state to the second surface area state.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: August 8, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Kitamura, Atsuko Sakata, Satoshi Wakatsuki
  • Publication number: 20170207236
    Abstract: According to one embodiment, an insulating layer is provided above a stairstep portion of a stacked body. A first cover film is provided between the stairstep portion and the insulating layer. The first cover film is of a material different from the insulating layer. A separation portion divides the stacked body and the insulating layer. A second cover film is provided at a side surface of the insulating layer on the separation portion side. The second cover film is of a material different from the insulating layer.
    Type: Application
    Filed: September 6, 2016
    Publication date: July 20, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki KITAMURA, Atsuko SAKATA, Satoshi WAKATSUKI, Takeshl ISHIZAKI, Daisuke IKENO, Tomotaka ARIGA
  • Publication number: 20170170065
    Abstract: A carbon film forming method including: forming a first carbon film so that the first carbon film is embedded in the step shape portion by supplying a film forming gas including a hydrocarbon-based carbon source gas to the process target object; etching the first carbon film so that a V-shaped etching region, which is wide in a frontage portion of the step shape portion and becomes narrow as going to a bottom portion of the step shape portion, is formed in the first carbon film existing within the step shape portion, by supplying an etching gas to the process target object; and forming a second carbon film so that the second carbon film is embedded in the etching region by supplying a film forming gas including a hydrocarbon-based carbon source gas to the process target object, in a state where the process target object is heated.
    Type: Application
    Filed: December 13, 2016
    Publication date: June 15, 2017
    Inventors: Masayuki KITAMURA, Akira SHIMIZU, Yosuke WATANABE
  • Patent number: 9673217
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a semiconductor body, and a stacked film. The stacked body includes a plurality of tungsten layers and a plurality of alloy layers of tungsten and molybdenum. At least portions of the tungsten layers are stacked with an air gap interposed. The alloy layers are provided on surfaces of the tungsten layers opposing the air gap. The semiconductor body extends in a stacking direction through the stacked body. The stacked film is provided between the semiconductor body and the tungsten layers. The stacked film includes a charge storage portion.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: June 6, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Yohei Sato, Yasuhito Yoshimizu, Satoshi Wakatsuki, Takeshi Ishizaki, Masayuki Kitamura, Daisuke Ikeno, Tomotaka Ariga, Junichi Wada, Hiroshi Tomita, Hisashi Okuchi, Ryohei Kitao, Toshiyuki Sasaki, Kazuhito Furumoto
  • Patent number: 9613872
    Abstract: A method of manufacturing a semiconductor device includes forming a first metal containing a first conductivity-type impurity above a substrate provided with a first conductivity-type impurity region containing the first conductivity-type impurity and a second conductivity-type impurity region containing a second conductivity-type impurity; and forming a metal silicide containing the first metal by selectively causing, by thermal treatment, a reaction between the first metal and silicon contained in the substrate in the first conductivity-type impurity region.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: April 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Wakatsuki, Masayuki Kitamura, Atsuko Sakata, Kyoichi Suguro
  • Patent number: 9613974
    Abstract: According to one embodiment, the contact electrode extends in the inter-layer insulating layer toward the second semiconductor region. The metal silicide film is in contact with the second semiconductor region and the contact electrode. The metal silicide film includes a first part and a second part. The first part is provided between a bottom of the contact electrode and the second semiconductor region. The second part is provided on a surface of the second semiconductor region between the first part and the gate electrode. A bottom of the second part is located at a position shallower than a bottom the first part.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: April 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroki Okamoto, Hiroshi Itokawa, Masayuki Kitamura, Atsushi Yagishita
  • Publication number: 20170092505
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched, the mask layer containing tungsten and boron, a composition ratio of the tungsten being not less than 30%, patterning the mask layer, and performing a dry etching to the layer to be etched using the mask layer being patterned, and forming a hole or a slit in the layer to be etched.
    Type: Application
    Filed: December 12, 2016
    Publication date: March 30, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinichi NAKAO, Shunsuke OCHIAI, Yusuke OSHIKI, Kei WATANABE, Mitsuhiro OMURA, Kosuke HORIBE, Atsuko SAKATA, Junichi WADA, Soichi YAMAZAKI, Masayuki KITAMURA, Yuya MATSUBARA