Patents by Inventor Masayuki Kitamura

Masayuki Kitamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170053869
    Abstract: According to one embodiment, the stacked body includes a plurality of metal films, a plurality of silicon oxide films, and a plurality of intermediate films. The intermediate films are provided between the metal films and the silicon oxide films. The intermediate films contain silicon nitride. Nitrogen composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the metal films than on sides of interfaces between the intermediate films and the silicon oxide films. Silicon composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the silicon oxide films than on sides of interfaces between the intermediate films and the metal films.
    Type: Application
    Filed: December 31, 2015
    Publication date: February 23, 2017
    Inventors: Atsuko SAKATA, Takeshi ISHIZAKI, Shinya OKUDA, Kei WATANABE, Masayuki KITAMURA, Satoshi WAKATSUKI, Daisuke IKENO, Junichi WADA, Hirotaka OGIHARA
  • Patent number: 9570464
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a first metal nitride film on a side surface of a hole extending in a stacking direction in a stacked body. The method includes forming a second metal nitride film on upper and lower surfaces of second layers and a side surface of the first metal nitride film. The method includes forming metal layers in first air gaps inside the second metal nitride film. The method includes removing the second layers and forming second air gaps between the metal layers. The method includes removing the first metal nitride film exposed to the second air gaps and dividing the first metal nitride film in the stacking direction.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: February 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Wakatsuki, Atsuko Sakata, Masayuki Kitamura, Daisuke Ikeno, Takeshi Ishizaki, Tomotaka Ariga
  • Patent number: 9512541
    Abstract: There is provided a selective growth method of selectively growing a thin film on exposed surfaces of an underlying insulation film and an underlying metal film, which includes: selectively growing a film whose thickness is decreased by combustion on the underlying metal film using metal of the underlying metal film as a catalyst; and selectively growing a silicon oxide film on the underlying insulation film while combusting the film whose thickness is decreased by combustion.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: December 6, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Akira Shimizu, Masayuki Kitamura
  • Patent number: 9484206
    Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a foundation layer including first and second layers being different from each other in material, and the foundation layer including a surface on which a boundary of the first and second layers is presented, a catalyst layer on the surface of the foundation layer, and the catalyst layer including a protruding area. The device further includes a graphene layer being in contact with the protruding area.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: November 1, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Taishi Ishikura, Akihiro Kajita, Tadashi Sakai, Atsunobu Isobayashi, Makoto Wada, Tatsuro Saito, Masayuki Kitamura, Atsuko Sakata
  • Publication number: 20160300845
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a film having semi-conductivity or conductivity, and a memory film. The stacked body includes a plurality of metal layers, a plurality of insulating layers, and a plurality of intermediate layers stacked on a major surface of the substrate. The film extends in the stacked body in a stacking direction of the stacked body. The memory film is provided between the film and the metal layers. The metal layers are tungsten layers and the intermediate layers are tungsten nitride layers. Or the metal layers are molybdenum layers and the intermediate layers are molybdenum nitride layers.
    Type: Application
    Filed: August 18, 2015
    Publication date: October 13, 2016
    Inventors: Takeshi ISHIZAKI, Junichi WADA, Atsuko SAKATA, Kei WATANABE, Masayuki KITAMURA, Daisuke IKENO, Satoshi WAKATSUKl, Hirotaka OGIHARA, Shinya OKUDA
  • Publication number: 20160276204
    Abstract: A method of manufacturing a semiconductor device uses a semiconductor manufacturing apparatus including a turn table allowing placement of at least first and second semiconductor substrates and being capable of moving positions of the first and the second semiconductor substrates by turning, a first film forming chamber, and a second film forming chamber. The first and the second film forming chambers are provided with an opening capable of loading and unloading the first and the second semiconductor substrates by lifting and lowering the first and the second semiconductor substrates placed on the turn table. The method includes transferring the first and the second semiconductor substrates between the first and the second film forming chambers by turning the turn fable and lifting and lowering the first and the second semiconductor substrates placed on the turn table; and forming a stack of films above the first and the second semiconductor substrates.
    Type: Application
    Filed: June 26, 2015
    Publication date: September 22, 2016
    Inventors: Atsuko SAKATA, Kei Watanabe, Junichi Wada, Masayuki Kitamura, Takeshi Ishizaki, Shinya Okuda, Hirotaka Ogihara, Satoshi Wakatsuki, Daisuke Ikeno
  • Publication number: 20160268285
    Abstract: According to one embodiment, the contact electrode extends in the inter-layer insulating layer toward the second semiconductor region. The metal silicide film is in contact with the second semiconductor region and the contact electrode. The metal silicide film includes a first part and a second part. The first part is provided between a bottom of the contact electrode and the second semiconductor region. The second part is provided on a surface of the second semiconductor region between the first part and the gate electrode. A bottom of the second part is located at a position shallower than a bottom the first part.
    Type: Application
    Filed: August 10, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroki OKAMOTO, Hiroshi Itokawa, Masayuki Kitamura, Atsushi Yagishita
  • Publication number: 20160268283
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers; a first electrode layer included in the plurality of electrode layers; a second electrode layer included in the plurality of electrode layers; a first insulating layer provided between the first electrode layer and the second electrode layer, and provided in contact with the first electrode layer and the second electrode layer; a semiconductor portion; a charge storage film; a first conductive film; and second conductive film. The first conductive film is provided between the first electrode layer and the charge storage film, and provided in contact with the first insulating layer. The second conductive film is provided between the second electrode layer and the charge storage film, and provided in contact with the first insulating layer.
    Type: Application
    Filed: July 9, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki KITAMURA, Atsuko Sakata, Satoshi Wakatsuki, Takeshi Ishizaki, Daisuke Ikeno, Junichi Wada, Kei Watanabe, Shinya Okuda, Hirotaka Ogihara, Hiroshi Nakazawa, Tomonori Aoyama, Kenji Aoyama, Hideaki Aochi
  • Publication number: 20160268210
    Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes interconnects each including a catalyst layer and a graphene layer thereon. The catalyst layer includes a first to fifth catalyst regions arranged along a first direction in order of the first to fifth catalyst regions. The first, third and fifth catalyst regions include upper surfaces higher than those of the second and fourth catalyst regions. Adjacent ones of the first to fifth catalyst regions are in contact with each other. A distance between the first and the third catalyst region and a distance between the third and fifth catalyst region are greater than a mean free path of graphene. The graphene layer includes a first graphene layer on the second catalyst region and a second graphene layer on the fourth catalyst region.
    Type: Application
    Filed: September 1, 2015
    Publication date: September 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuro SAITO, Masayuki KITAMURA, Atsuko SAKATA, Makoto WADA, Akihiro KAJITA, Tadashi SAKAI
  • Patent number: 9443805
    Abstract: A wire of an embodiment includes: a substrate; a metal film provided on the substrate; a metal part provided on the metal film; and graphene wires formed on the metal part, wherein the graphene wire is electrically connected to the metal film, and the metal film and the metal part are formed using different metals or alloys from each other.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: September 13, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Yamazaki, Makoto Wada, Masayuki Kitamura, Tadashi Sakai
  • Publication number: 20160251755
    Abstract: A method for forming a carbon film on a process surface to be processed of a workpiece includes forming a seed layer on the process surface of the workpiece by supplying an aminosilane-based gas, an aminosilane-based gas having high-order equal to or higher than that of aminodisilane, or a nitrogen-containing heterocyclic compound gas onto the process surface; and forming the carbon film on the process surface on which the seed layer is formed by supplying a hydrocarbon-based carbon source gas and a thermal decomposition temperature lowering gas for lowering a thermal decomposition temperature of the hydrocarbon-based carbon source gas onto the process surface on which the seed layer is obtained, and by setting a film formation temperature to be lower than the thermal decomposition temperature of the hydrocarbon-based carbon source gas.
    Type: Application
    Filed: February 17, 2016
    Publication date: September 1, 2016
    Inventors: Masayuki KITAMURA, Satoshi MIZUNAGA, Akira SHIMIZU, Akinobu KAKIMOTO
  • Patent number: 9431345
    Abstract: According to one embodiment, a semiconductor device includes a metal interconnect and a graphene interconnect which are stacked to one another.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: August 30, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Masayuki Kitamura, Makoto Wada, Masayuki Katagiri, Yuichi Yamazaki, Akihiro Kajita
  • Patent number: 9418938
    Abstract: A semiconductor device includes a graphene interconnect, an insulation film formed on the graphene interconnect, and a via conducting portion formed in a via hole provided in the graphene interconnect and the insulation film. The graphene interconnect has a region containing an impurity at least around the via hole.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: August 16, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Kitamura, Atsuko Sakata, Hisao Miyazaki, Akihiro Kajita, Tadashi Sakai
  • Patent number: 9406694
    Abstract: According to one embodiment, a semiconductor device includes a metal layer containing boron, a semiconductor film extending in a direction intersecting with a direction in which the metal layer extends, a charge storage film provided between the semiconductor film and the metal layer, a first dielectric film provided between the charge storage film and the metal layer, and a nitride film provided between the first dielectric film and the metal layer. The nitride film includes a first titanium nitride film provided in contact with the first dielectric film, a second titanium nitride film provided in contact with the metal layer, and an amorphous nitride film provided between the first titanium nitride film and the second titanium nitride film.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: August 2, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daisuke Ikeno, Masayuki Kitamura, Atsuko Sakata
  • Patent number: 9404880
    Abstract: The sensor includes a first graphene film that is provided on the insulating layer so as to be located in a flow path of a liquid containing the detection target substance, the first graphene film having a first edge that is parallel with a first direction that is along the flow path and a first edge that is parallel with a second direction that is different from the first direction, and the first graphene film having the shape of a band that extends in the second direction. The sensor includes a first electrode that is electrically connected to the first edge of the first graphene film that is parallel with the first direction. The sensor includes a second electrode that is electrically connected to a second edge of the first graphene film that is opposed to the first edge that is parallel with the first direction.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: August 2, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuro Saito, Masayuki Kitamura, Atsuko Sakata, Akihiro Kajita, Atsunobu Isobayashi, Tadashi Sakai
  • Publication number: 20160126106
    Abstract: There is provided a selective growth method of selectively growing a thin film on exposed surfaces of an underlying insulation film and an underlying metal film, which includes: selectively growing a film whose thickness is decreased by combustion on the underlying metal film using metal of the underlying metal film as a catalyst; and selectively growing a silicon oxide film on the underlying insulation film while combusting the film whose thickness is decreased by combustion.
    Type: Application
    Filed: October 20, 2015
    Publication date: May 5, 2016
    Inventors: Akira SHIMIZU, Masayuki KITAMURA
  • Publication number: 20160093538
    Abstract: A method of manufacturing a semiconductor device includes forming a first metal containing a first conductivity-type impurity above a substrate provided with a first conductivity-type impurity region containing a first conductivity-type impurity and a second conductivity-type impurity region containing a second conductivity-type impurity; and forming a metal silicide containing the first metal by selectively causing, by thermal treatment, a reaction between the first metal and silicon contained in the substrate in the first conductivity-type impurity region.
    Type: Application
    Filed: March 4, 2015
    Publication date: March 31, 2016
    Inventors: SATOSHI WAKATSUKI, MASAYUKI KITAMURA, ATSUKO SAKATA, KYOICHI SUGURO
  • Publication number: 20160093542
    Abstract: A method of manufacturing a semiconductor device includes forming a film along a surface of a semiconductor substrate in a first state having a first surface area by supplying a reaction gas at a first flow rate. The method further includes detecting a transition from the first state to a second state having a second surface area different from the first surface area. The method still further includes forming a film by changing the flow rate of the reaction gas from the first flow rate to a second flow rate different form the first flow rate after detecting the transition from the first state to the second state.
    Type: Application
    Filed: March 2, 2015
    Publication date: March 31, 2016
    Inventors: MASAYUKI KITAMURA, Atsuko Sakata, Satoshi Wakatsuki
  • Publication number: 20160079176
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a first film having a first melting point, forming a pattern of a second film on an upper surface of the first film, the second film having a second melting point lower than the first melting point, and forming a graphene film on the upper surface of the first film, the graphene film being formed from a side surface of the pattern of the second film.
    Type: Application
    Filed: March 12, 2015
    Publication date: March 17, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsunobu ISOBAYASHI, Masayuki KITAMURA, Yuichi YAMAZAKI, Akihiro KAJITA, Tatsuro SAITO, Taishi ISHIKURA, Atsuko SAKATA, Tadashi SAKAI, Makoto WADA
  • Publication number: 20160071803
    Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a first interconnect, and an insulating film provided on the first interconnect, and being with a through hole communicating with the first interconnect. A catalyst layer is provided on the first interconnect of a bottom portion of the through hole. The catalyst layer has a form of a continuous film, and includes catalyst material and impurity. A first plug is provided in the through hole and is in contact with the catalyst layer, and includes a carbon nanotube layer. A second interconnect is disposed above the first interconnect and connected to the first interconnect via the first plug.
    Type: Application
    Filed: March 11, 2015
    Publication date: March 10, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuro SAITO, Masayuki KITAMURA, Yuichi YAMAZAKI, Akihiro KAJITA, Atsuko SAKATA, Tadashi SAKAI