Patents by Inventor Matthew W. Copel

Matthew W. Copel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9881759
    Abstract: A piezoelectronic switch device for radio frequency (RF) applications includes a piezoelectric (PE) material layer and a piezoresistive (PR) material layer separated from one another by at least one electrode, wherein an electrical resistance of the PR material layer is dependent upon an applied voltage across the PE material layer by way of an applied pressure to the PR material layer by the PE material layer; and a conductive, high yield material (C-HYM) comprising a housing that surrounds the PE material layer, the PR material layer and the at least one electrode, the C-HYM configured to mechanically transmit a displacement of the PE material layer to the PR material layer such that applied voltage across the PE material layer causes an expansion thereof and an increase the applied pressure to the PR material layer, thereby causing a decrease in the electrical resistance of the PR material layer.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: January 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew W. Copel, Bruce G. Elmegreen, Glenn J. Martyna, Dennis M. Newns, Thomas M. Shaw, Paul M. Solomon
  • Patent number: 9659249
    Abstract: Technical solutions are described for forming a semiconductor device for a crosspoint array that implements a pre-programmed neural network. An example method includes sequentially depositing a semiconducting layer, a top insulating layer, and a shunting layer onto a base insulating layer. The method further includes etching selective portions of the top insulating layer corresponding to resistance values associated with weights of the crossbar that implements the neural network.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: May 23, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Matthew W. Copel
  • Publication number: 20170084413
    Abstract: A piezoelectronic switch device for radio frequency (RF) applications includes a piezoelectric (PE) material layer and a piezoresistive (PR) material layer separated from one another by at least one electrode, wherein an electrical resistance of the PR material layer is dependent upon an applied voltage across the PE material layer by way of an applied pressure to the PR material layer by the PE material layer; and a conductive, high yield material (C-HYM) comprising a housing that surrounds the PE material layer, the PR material layer and the at least one electrode, the C-HYM configured to mechanically transmit a displacement of the PE material layer to the PR material layer such that applied voltage across the PE material layer causes an expansion thereof and an increase the applied pressure to the PR material layer, thereby causing a decrease in the electrical resistance of the PR material layer.
    Type: Application
    Filed: June 22, 2015
    Publication date: March 23, 2017
    Inventors: Matthew W. Copel, Bruce G. Elmegreen, Glenn J. Martyna, Dennis M. Newns, Thomas M. Shaw, Paul M. Solomon
  • Patent number: 9472368
    Abstract: A piezoelectronic switch device for radio frequency (RF) applications includes a piezoelectric (PE) material layer and a piezoresistive (PR) material layer separated from one another by at least one electrode, wherein an electrical resistance of the PR material layer is dependent upon an applied voltage across the PE material layer by way of an applied pressure to the PR material layer by the PE material layer; and a conductive, high yield material (C-HYM) comprising a housing that surrounds the PE material layer, the PR material layer and the at least one electrode, the C-HYM configured to mechanically transmit a displacement of the PE material layer to the PR material layer such that applied voltage across the PE material layer causes an expansion thereof and an increase the applied pressure to the PR material layer, thereby causing a decrease in the electrical resistance of the PR material layer.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew W. Copel, Bruce G. Elmegreen, Glenn J. Martyna, Dennis M. Newns, Thomas M. Shaw, Paul M. Solomon
  • Publication number: 20160268083
    Abstract: A piezoelectronic switch device for radio frequency (RF) applications includes a piezoelectric (PE) material layer and a piezoresistive (PR) material layer separated from one another by at least one electrode, wherein an electrical resistance of the PR material layer is dependent upon an applied voltage across the PE material layer by way of an applied pressure to the PR material layer by the PE material layer; and a conductive, high yield material (C-HYM) comprising a housing that surrounds the PE material layer, the PR material layer and the at least one electrode, the C-HYM configured to mechanically transmit a displacement of the PE material layer to the PR material layer such that applied voltage across the PE material layer causes an expansion thereof and an increase the applied pressure to the PR material layer, thereby causing a decrease in the electrical resistance of the PR material layer.
    Type: Application
    Filed: May 25, 2016
    Publication date: September 15, 2016
    Inventors: Matthew W. Copel, Bruce G. Elmegreen, Glenn J. Martyna, Dennis M. Newns, Thomas M. Shaw, Paul M. Solomon
  • Patent number: 9419201
    Abstract: A semiconductor device, a piezoelectronic transistor (PET) device, and a method of fabricating the PET device are described. The method includes forming a first stack of dielectric layers, forming a first metal layer over the first stack, forming a piezoelectric (PE) material on the first metal layer, and forming a second metal layer on the PE material. The method also includes forming a piezoresistive (PR) element on the second metal layer through a gap in a first membrane formed a distance d above the second metal layer.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: August 16, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian A. Bryce, Josephine B. Chang, Matthew W. Copel, Marcelo A. Kuroda
  • Patent number: 9419203
    Abstract: A method of forming a piezoelectronic transistor (PET) device, the PET device, and a semiconductor including the PET device are described. The method includes forming a first metal layer, forming a layer of a piezoelectric (PE) element on the first metal layer, and forming a second metal layer on the PE element. The method also includes forming a well above the second metal layer, forming a piezoresistive (PR) material in the well and above the well, and forming a passivation layer and a top metal layer above the PR material at the diameter of the PR material above the well, wherein a cross sectional shape of the well, the PR material above the well, the passivation layer, and the top metal layer is a T-shaped structure. The method further includes forming a metal clamp layer as a top layer of the PET device.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: August 16, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian A. Bryce, Josephine B. Chang, Matthew W. Copel, Marcelo A. Kuroda
  • Publication number: 20160126446
    Abstract: A method of forming a piezoelectronic transistor (PET) device, the PET device, and a semiconductor including the PET device are described. The method includes forming a first metal layer, forming a layer of a piezoelectric (PE) element on the first metal layer, and forming a second metal layer on the PE element. The method also includes forming a well above the second metal layer, forming a piezoresistive (PR) material in the well and above the well, and forming a passivation layer and a top metal layer above the PR material at the diameter of the PR material above the well, wherein a cross sectional shape of the well, the PR material above the well, the passivation layer, and the top metal layer is a T-shaped structure. The method further includes forming a metal clamp layer as a top layer of the PET device.
    Type: Application
    Filed: June 23, 2015
    Publication date: May 5, 2016
    Inventors: Brian A. Bryce, Josephine B. Chang, Matthew W. Copel, Marcelo A. Kuroda
  • Publication number: 20160126044
    Abstract: A piezoelectronic switch device for radio frequency (RF) applications includes a piezoelectric (PE) material layer and a piezoresistive (PR) material layer separated from one another by at least one electrode, wherein an electrical resistance of the PR material layer is dependent upon an applied voltage across the PE material layer by way of an applied pressure to the PR material layer by the PE material layer; and a conductive, high yield material (C-HYM) comprising a housing that surrounds the PE material layer, the PR material layer and the at least one electrode, the C-HYM configured to mechanically transmit a displacement of the PE material layer to the PR material layer such that applied voltage across the PE material layer causes an expansion thereof and an increase the applied pressure to the PR material layer, thereby causing a decrease in the electrical resistance of the PR material layer.
    Type: Application
    Filed: October 31, 2014
    Publication date: May 5, 2016
    Inventors: Matthew W. Copel, Bruce G. Elmegreen, Glenn J. Martyna, Dennis M. Newns, Thomas M. Shaw, Paul M. Solomon
  • Publication number: 20160126448
    Abstract: A semiconductor device, a piezoelectronic transistor (PET) device, and a method of fabricating the PET device are described. The method includes forming a first stack of dielectric layers, forming a first metal layer over the first stack, forming a piezoelectric (PE) material on the first metal layer, and forming a second metal layer on the PE material. The method also includes forming a piezoresistive (PR) element on the second metal layer through a gap in a first membrane formed a distance d above the second metal layer.
    Type: Application
    Filed: June 23, 2015
    Publication date: May 5, 2016
    Inventors: Brian A. Bryce, Josephine B. Chang, Matthew W. Copel, Marcelo A. Kuroda
  • Patent number: 9293687
    Abstract: A method of forming a piezoelectronic transistor (PET) device, the PET device, and a semiconductor including the PET device are described. The method includes forming a first metal layer, forming a layer of a piezoelectric (PE) element on the first metal layer, and forming a second metal layer on the PE element. The method also includes forming a well above the second metal layer, forming a piezoresistive (PR) material in the well and above the well, and forming a passivation layer and a top metal layer above the PR material at the diameter of the PR material above the well, wherein a cross sectional shape of the well, the PR material above the well, the passivation layer, and the top metal layer is a T-shaped structure. The method further includes forming a metal clamp layer as a top layer of the PET device.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: March 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Brian A. Bryce, Josephine B. Chang, Matthew W. Copel, Marcelo A. Kuroda
  • Patent number: 9263664
    Abstract: A semiconductor device, a piezoelectronic transistor (PET) device, and a method of fabricating the PET device are described. The method includes forming a first stack of dielectric layers, forming a first metal layer over the first stack, forming a piezoelectric (PE) material on the first metal layer, and forming a second metal layer on the PE material. The method also includes forming a piezoresistive (PR) element on the second metal layer through a gap in a first membrane formed a distance d above the second metal layer.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Brian A. Bryce, Josephine B. Chang, Matthew W. Copel, Marcelo A. Kuroda
  • Publication number: 20150126025
    Abstract: A gate stack for a transistor is formed by a process including forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer.
    Type: Application
    Filed: January 16, 2015
    Publication date: May 7, 2015
    Inventors: Takashi ANDO, Kisik CHOI, Matthew W. COPEL, Richard A. HAIGHT
  • Patent number: 8975174
    Abstract: A gate stack for a transistor is formed by a process including forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Kisik Choi, Matthew W. Copel, Richard A. Haight
  • Patent number: 8803141
    Abstract: A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: David B. Mitzi, Matthew W. Copel
  • Patent number: 8791004
    Abstract: A non-transitory computer readable medium encoded with a program for fabricating a gate stack for a transistor is disclosed. The program includes instructions configured to perform a method. The method includes forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: July 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Kisik Choi, Matthew W. Copel, Richard A. Haight
  • Patent number: 8735243
    Abstract: A method for fabricating an FET device is disclosed. The FET device has a gate insulator with a high-k dielectric portion, and a threshold modifying material. The method introduces a stabilizing material into the gate insulator in order to hinder one or more metals from the threshold modifying material to penetrate across the high-k portion of the gate insulator. The introduction of the stabilizing material may involve disposing a stabilizing agent over a layer which contains an oxide of the one or more metals. A stabilizing material may also be incorporated into the high-k dielectric. Application of the method may lead to FET devices with unique gate insulator structures.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Matthew W. Copel, Bruce B. Doris, Vijay Narayanan, Yun-Yu Wang
  • Publication number: 20140113416
    Abstract: A method for fabricating a carbon-based semiconductor device. A substrate is provided and source/drain contacts are formed on the substrate. A graphene channel is formed on the substrate connecting the source contact and the drain contact. A dielectric layer is formed on the graphene channel with a molecular beam deposition process. A gate contact is formed over the graphene channel and on the dielectric. The gate contact is in a non-overlapping position with the source and drain contacts leaving exposed sections of the graphene channel between the gate contact and the source and drain contacts.
    Type: Application
    Filed: June 28, 2012
    Publication date: April 24, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nestor A. BOJARCZUK, Matthew W. COPEL, Yu-ming LIN
  • Publication number: 20140001440
    Abstract: A carbon-based semiconductor device includes a substrate, source/drain contacts, a graphene channel, a dielectric layer, and a gate. The source/drain contacts are formed on the substrate. The graphene channel is formed on the substrate connecting the source contact and the drain contact. The dielectric layer is formed on the graphene channel with a molecular beam deposition process. The gate contact is formed over the graphene channel and on the dielectric. The gate contact is in a non-overlapping position with the source and drain contacts leaving exposed sections of the graphene channel between the gate contact and the source and drain contacts.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 2, 2014
    Applicant: International Business Machines Corporation
    Inventors: Nestor A. BOJARCZUK, Matthew W. COPEL, Yu-ming LIN
  • Publication number: 20130277751
    Abstract: A gate stack for a transistor is formed by a process including forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer.
    Type: Application
    Filed: June 24, 2013
    Publication date: October 24, 2013
    Inventors: Takashi ANDO, Kisik CHOI, Matthew W. COPEL, Richard A. HAIGHT