Abstract: A read-only memory cell (ROM) and a fabrication method thereof. The cell comprises a substrate, a plurality of bit lines, a plurality of bit line oxides, a gate dielectric layer and a word line. The bit lines are formed near the surface of the substrate. The bit line oxides are disposed over the bit lines. The gate dielectric layer is disposed over the substrate between the bit lines and further comprises a silicon-rich oxide layer. The word line is disposed over the bit line oxides and the gate dielectric layer.

Abstract: In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

Abstract: An apparatus and method for accessing data from a storage medium is disclosed. The apparatus fetches a data block from the storage medium via an accessing unit, and corrects an error of the data block by an error correction code (ECC) decoder according to an ECC of the data block. The apparatus also includes an error detection code (EDC) processor for calculating an EDC of each data sector of the data block, and a flag register for storing a flag associated with each data sector. The method includes re-fetching a data sector if the associated flag indicates the EDC of the data sector is incorrect; and bypassing a data sector if the associated flag indicates that the EDC of the data sector is correct, even though the ECC of the data block indicates that the data sector contains an error.

Abstract: A multi-bit vertical memory cell and method of fabricating the same. The multi-bit vertical memory cell comprises a semiconductor substrate with a trench, a plurality of bit lines formed therein near its surface and the bottom trench respectively, a plurality of bit line insulating layers over each bit line, a silicon rich oxide layer conformably formed on the sidewall of the trench and the surface of the surface of the bit line insulating layer, and a word line over the silicon rich oxide layer, and the trench is filled with the word line.

Abstract: A read-only memory cell (ROM) and a fabrication method thereof. The cell comprises a substrate, a plurality of bit lines, a plurality of bit line oxides, a gate dielectric layer and a word line. The bit lines are formed near the surface of the substrate. The bit line oxides are disposed over the bit lines. The gate dielectric layer is disposed over the substrate between the bit lines and further comprises a silicon-rich oxide layer. The word line is disposed over the bit line oxides and the gate dielectric layer.

Abstract: The invention discloses an ESD (Electro Static Discharge) protection circuit, including a resistor device, a capacitor device and a PMOS device. The resistor device is connected in series between a power supply and the capacitor device. The capacitor device is connected in series between the resistor device and the ground. A gate electrode of the PMOS device is connected between the resistor device and the capacitor device. A bulk electrode of the PMOS device is interconnected to a first electrode of the PMOS device, and the first electrode is connected to the power supply. Alternatively, another ESD protection circuit for multiple power supplies includes at least two aforementioned ESD protection circuits, and a common ESD bus. The ESD protection circuits are connected to separate power supplies, and both connected to the common ESD bus. By using the ESD protection circuit, there is no noise between the separate power supplies, and an ESD current could be discharged easily and safely.

Abstract: A gate-equivalent-potential circuit and method for an I/O pad ESD protection arrangement including used and unused MOS fingers connected to the I/O pad comprises a switch connected between the gates of the MOS fingers, an ESD detector connected to the switch to turn on the switch upon an ESD event and a gate-modulated circuit connected to the gate of the unused finger to couple a voltage thereto to reduce the triggering voltage of the transistors within the fingers.

Abstract: An optical storage system includes a pickup head for picking up data from a storage medium. Firstly, the maxima of a tracking error signal and runout are obtained in a calibration procedure in a close loop formed by an optical pickup head, a pre-amplifier, a compensator, a band-pass filter and a maximum detector. A calibration factor is then defined and derived by using the obtained maxima and nominal factors of a power amplifier and the optical pickup head of the optical storage system. The path formed by the series-connected band-pass filter and maximum detector is then disabled, while the calculated calibration factor is then stored in the compensator. The optical storage system may operate in a close loop formed by the optical pick head, pre-amplifier, compensator, a power amplifier under a normal operation procedure so that the optical storage system may record or read data onto/from an optical disc under the compensation provided by the calibration factor.

Abstract: An I/O pad ESD protection circuit is composed of a SCR circuit, a first diode, a second diode, and an anti-latch-up circuit. The SCR circuit has a first connection terminal and a second connection terminal, respectively coupled to the I/O pad and the ground voltage, so as to discharge the electrostatic charges. The anti-latch-up circuit has two terminals, which are respectively coupled to the voltage source and the ground voltage, and another connection terminal, used to send an anti-latch-up signal to the SCR for changing the activating rate. The latch-up phenomenon is avoided.

Abstract: A pad circuit and operating method for automatically adjusting gains is disclosed, wherein the pad circuit is embedded in an integrated circuit chip that further includes a core logic circuit therein. The pad circuit includes an input/output pin, a gain-adjustable output buffer, an input buffer and a signal feature detector. The method includes the steps as follows. A test signal is firstly issued from the core logic circuit to the gain-adjustable output buffer, while the test signal is then manipulated and outputted to an external device via the input/output pin. Next, a feedback test signal is fed into the input buffer from the external device, while a test result is realized according to a waveform feature of the feedback test signal. Finally, the gain of the gain-adjustable output buffer is adjusted according to the obtained test result.

Abstract: The present invention provides a PMSCR (bridging modified lateral modified silicon controlled rectifier having first conductivity type) with a guard ring controlled circuit. The present invention utilizes controlled circuit such as switch to control functionally of guard ring of PMSCR. In normal operation, the switch is of low impedance such that the guard ring is short to anode and collects electrons to enhance the power-zapping immunity. Furthermore, during the ESD (electrostatic discharge) event, the switch is of high impedance such that the guard ring is non-functional. Thus, the PMSCR with guard ring control circuit can enhance both the ESD performance and the power-zapping immunity in the application of the HV (high voltage) pad.

Abstract: A charge pump circuit is provided. The charge pump circuit includes a plurality of voltage-boosting stages connected in series with each other and having a supply terminal, a control terminal, and an output terminal respectively, and a plurality of voltage multipliers, each multiplier having an input terminal, a first output terminal for outputting a first clock signal, and a second output terminal for outputting a second clock signal respectively, wherein the input terminal of a first voltage multiplier is coupled to a clock signal, a magnitude of the first clock signal is a multiple of a magnitude of the second clock signal, each of the voltage multipliers is coupled the respective second output terminal thereof to the input terminal of a downstream voltage multiplier, and the first output terminal of the voltage multiplier is coupled to the control terminal of a respective one of the voltage-boosting stages.

Abstract: The present invention provides a stack-gate flash memory array. In the present invention, one bit line for a conventional memory cell had been divided two independent bit lines; two word lines have been combined together via the gate terminal of an isolated transistor. Because the bit lines are divided and the word lines will stop the leakage current via the isolated transistor, the leakage current would not affect the other memory cells. Hence, the present invention can avoid the data inaccuracy due to the leakage current resulting from the erratic bits, and thus can extend the flash memory's lifetime.

Abstract: A flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, and a source/drain region. The floating gate, disposed over the substrate and insulated from the substrate, has a plurality of hut structures. The control gate is disposed over the floating gate and insulated from the floating gate. The source/drain region is formed in the substrate. This invention further includes a method of fabricating a flash memory cell. First, a polysilicon layer and a germanium layer are successively formed over a substrate and insulated from the substrate. Subsequently, the substrate is annealed to form a germanium layer having a plurality of hut structures on the polysilicon layer to serve as a floating gate with the polysilicon layer. Next, a control gate is formed over the floating gate and insulated from the floating gate. Finally, a source/drain region is formed in the substrate.

Abstract: An electrostatic discharge (ESD) device used with a high-voltage input pad is described. The ESD device serves as a secondary device of a two-stage protection circuit, and comprises a substrate, a first MOS transistor and a second MOS transistor. The first MOS transistor is disposed on the substrate and comprises a first gate, a first drain and a first source, wherein the first gate is coupled to a bias Vg1, and the first drain is coupled to the high-voltage input pad. The second MOS transistor is disposed on the substrate and comprises a second gate, a second drain and a second source, wherein the second gate and the second source are both grounded, and the second drain is electrically connected with the first source of the first MOS transistor.

Abstract: The present invention provides a PMSCR (bridging modified lateral modified silicon controlled rectifier having first conductivity type) with a guard ring controlled circuit. The present invention utilizes controlled circuit such as switch to control functionally of guard ring of PMSCR. In normal operation, the switch is of low impedance such that the guard ring is short to anode and collects electrons to enhance the power-zapping immunity. Furthermore, during the ESD (electrostatic discharge) event, the switch is of high impedance such that the guard ring is non-functional. Thus, the PMSCR with guard ring control circuit can enhance both the ESD performance and the power-zapping immunity in the application of the HV (high voltage) pad.

Abstract: An ESD protection apparatus for a high-voltage input pad comprises a modulator connected between the input pad and a snapback device with first and second guard rings surrounding the modulator, third guard ring surrounding the snapback device, and first and second guard ring control circuits to control the guard rings such that the protection apparatus has higher triggering and holding voltages under normal operation and lower triggering and holding voltages under ESD event.

Abstract: A flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, and a source/drain region. The floating gate, disposed over the substrate and insulated from the substrate, has a plurality of hut structures. The control gate is disposed over the floating gate and insulated from the floating gate. The source/drain region is formed in the substrate. This invention further includes a method of fabricating a flash memory cell. First, a polysilicon layer and a germanium layer are successively formed over a substrate and insulated from the substrate. Subsequently, the substrate is annealed to form a germanium layer having a plurality of hut structures on the polysilicon layer to serve as a floating gate with the polysilicon layer. Next, a control gate is formed over the floating gate and insulated from the floating gate. Finally, a source/drain region is formed in the substrate.

Abstract: An ESD protection apparatus for dual-polarity input pad comprises a triple-well formed with a first, second and third regions to form an SCR structure. A first and second ground connection regions of opposite conductivity types are formed on the first region, a first and second input connection regions of opposite conductivity types are formed in the third region, and a bridge region is formed across the second region and extends to the first and third regions. Under normal operation, the first, second, and third regions form two back-to-back diodes. Under positive polarity ESD event, breakdown is occurred between the bridge and first regions to thereby trigger an SCR circuit for positive polarity ESD protection. Under negative polarity ESD event, breakdown is occurred between the bridge and third regions to thereby trigger an SCR circuit for negative polarity ESD protection.

Abstract: The present invention provides a PMSCR (bridging modified lateral modified silicon controlled rectifier having first conductivity type) with a guard ring controlled circuit. The present invention utilizes controlled circuit such as switch to control functionally of guard ring of PMSCR. In normal operation, the switch is of low impedance such that the guard ring is short to anode and collects electrons to enhance the power-zapping immunity. Furthermore, during the ESD (electrostatic discharge) event, the switch is of high impedance such that the guard ring is non-functional. Thus, the PMSCR with guard ring control circuit can enhance both the ESD performance and the power-zapping immunity in the application of the HV (high voltage) pad.