Abstract: The present invention provides a PMSCR (bridging modified lateral modified silicon controlled rectifier having first conductivity type) with a guard ring controlled circuit. The present invention utilizes controlled circuit such as switch to control functionally of guard ring of PMSCR. In normal operation, the switch is of low impedance such that the guard ring is short to anode and collects electrons to enhance the power-zapping immunity. Furthermore, during the ESD (electrostatic discharge) event, the switch is of high impedance such that the guard ring is non-functional. Thus, the PMSCR with guard ring control circuit can enhance both the ESD performance and the power-zapping immunity in the application of the HV (high voltage) pad.

Abstract: An ESD protection device. The ESD protection device is set between a memory device, a second voltage level and a pad coupled to a first voltage level. The ESD protection device includes a first second type doped region formed on the first type substrate and coupled to the first voltage level, a second second type doped region formed on the first type substrate and coupled to the second voltage level, a third second type doped region formed on the first type substrate, a second type well formed between the first second type doped region and the third second type doped region, and an isolation element formed between the second second type doped region and the third second type doped region.

Abstract: A gate-equivalent-potential circuit and method for an I/O pad ESD protection arrangement including used and unused MOS fingers connected to the I/O pad comprises a switch connected between the gates of the MOS fingers, an ESD detector connected to the switch to turn on the switch upon an ESD event and a gate-modulated circuit connected to the gate of the unused finger to couple a voltage thereto to reduce the triggering voltage of the transistors within the fingers.

Abstract: A substrate pump circuit and method for I/O ESD protection including NMOS fingers connected to the interconnection between an I/O pad and an internal circuit comprises a MOS device connected to the interconnection between the I/O pad and the internal circuit and the substrate under the control of a switch to turn it on to conduct a pumping current through the substrate resistor when the I/O pad is under ESD stress, so as to pull up the potential of the substrate adjacent to the NMOS fingers, resulting in the reduction of the triggering voltage of the NMOS fingers.

Abstract: The present invention provides a method for forming a floating gate with a poly tip. The method includes the step of providing a semiconductor substrate with a gate dielectric layer formed on the semiconductor substrate. A first polysilicon layer is then formed on the gate dielectric layer. A hard mask layer is formed on the first polysilicon layer. Then, an opening is formed in the hard mask layer to expose a portion of the first polysilicon layer. Next, a poly spacer is formed in the opening. Then, the hard mask layer and the first polysilicon layer thereunder are removed to form the floating gate.

Abstract: The present invention provides a method for forming a floating gate with a poly tip. The method includes the step of providing a semiconductor substrate with a gate dielectric layer formed on the semiconductor substrate. A first polysilicon layer is then formed on the gate dielectric layer. A hard mask layer is formed on the first polysilicon layer. Then, an opening is formed in the hard mask layer to expose a portion of the first polysilicon layer. Next, a poly spacer is formed in the opening. Then, the hard mask layer and the first polysilicon layer thereunder are removed to form the floating gate.

Abstract: A flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, and a source/drain region. The floating gate, disposed over the substrate and insulated from the substrate, has a plurality of hut structures. The control gate is disposed over the floating gate and insulated from the floating gate. The source/drain region is formed in the substrate. This invention further includes a method of fabricating a flash memory cell. First, a polysilicon layer and a germanium layer are successively formed over a substrate and insulated from the substrate. Subsequently, the substrate is annealed to form a germanium layer having a plurality of hut structures on the polysilicon layer to serve as a floating gate with the polysilicon layer. Next, a control gate is formed over the floating gate and insulated from the floating gate. Finally, a source/drain region is formed in the substrate.

Abstract: An electrostatic discharge (ESD) protection circuit is disclosed. This invention relates an electrostatic discharge protection circuit for multi-power and mixed-voltage integrated circuit. In the electrostatic discharge protection circuit of the invention, an ESD protection cell formed with voltage selector, control circuit and transistor is used to connect with a independent power and ESD bus is used to connect with each ESD protection cell so that each power is isolated from each other during normal operation. Therefore, each power can be operated independently and circuit will be prevented from ESD during ESD discharging.

Abstract: A pad circuit and operating method for automatically adjusting gains is disclosed, wherein the pad circuit is embedded in an integrated circuit chip that further includes a core logic circuit therein. The pad circuit includes an input/output pin, a gain-adjustable output buffer, an input buffer and a signal feature detector. The method includes the steps as follows. A test signal is firstly issued from the core logic circuit to the gain-adjustable output buffer, while the test signal is then manipulated and outputted to an external device via the input/output pin. Next, a feedback test signal is fed into the input buffer from the external device, while a test result is realized according to a waveform feature of the feedback test signal. Finally, the gain of the gain-adjustable output buffer is adjusted according to the obtained test result.

Abstract: A charge pump circuit is provided. The charge pump circuit includes at least one voltage-boosting stage connected in series with each other and having a supply terminal, a control terminal, and an output terminal respectively, and at least one voltage multiplier having an input terminal, a first output terminal for outputting a first clock signal, and a second output terminal for outputting a second clock signal respectively, wherein the input terminal of a first voltage multiplier is coupled to a clock signal, the first clock signal is a voltage-multiplying signal of the second clock signal, each of the voltage multipliers is coupled the respective second output terminal thereof to the input terminal of a downstream voltage multiplier, and the first output terminal of the voltage multiplier is coupled to the control terminal of a respective one of the voltage-boosting stage.

Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure of the present invention uses a resistance capacitance (RC) circuit to distinguish an overshoot phenomenon caused by the instantaneous power-on from an ESD event, so as to prevent the ESD protection device, such as a P-type modified lateral silicon controlled rectifier (MLSCR), from being triggered unexpectedly by an overshoot phenomenon which results from the power-on under normal operation, and thereby the efficiency of the ESD protection device is promoted.

Abstract: A method of forming emitter tips on a field emission display. A conductive layer is formed on a substrate, and then a photoresist layer is formed on the conductive layer wherein the photoresist layer has at least a pattern for defining predetermined areas of the emitter tips. Next, using plasma etching with the pattern of the photoresist layer as a mask, the conductive layer is etched to become a plurality of emitter stages. The etching rate of the conductive layer is greater than the etching rate of the photoresist layer. Finally, continuous use of plasma etching with an increased vertical-etching rate etches the lateral sidewalls of the emitter stages, thus shaping them as emitter tips.

Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure of the present invention uses a resistance capacitance (RC) circuit to distinguish an overshoot phenomenon caused by the instantaneous power-on from an ESD event, so as to prevent the ESD protection device, such as P-type modified lateral silicon controlled rectifier (MLSCR), from being triggered unexpectedly by an overshoot phenomenon resulted from the power-on under normal operation, and thereby the efficiency of the ESD protection device is promoted.

Abstract: The invention discloses an ESD (Electro Static Discharge) protection circuit, including a resistor device, a capacitor device and a PMOS device. The resistor device is connected in series between a power supply and the capacitor device. The capacitor device is connected in series between the resistor device and the ground. A gate electrode of the PMOS device is connected between the resistor device and the capacitor device. A bulk electrode of the PMOS device is interconnected to a first electrode of the PMOS device, and the first electrode is connected to the power supply. Alternatively, another ESD protection circuit for multiple power supplies includes at least two aforementioned ESD protection circuits, and a common ESD bus. The ESD protection circuits are connected to separate power supplies, and both connected to the common ESD bus. By using the ESD protection circuit, there is no noise between the separate power supplies, and an ESD current could be discharged easily and safely.

Abstract: A phase comparator for calculating the phase difference between a test wave form and an output wave form in a disk drive includes a phase converter, a first multiplier, a first integrator, a second multiplier, a second integrator and a phase angle calculator. The phase converter for delaying the test wave form for a specific time based on the frequency thereof. The first multiplier electrically coupled to the phase converter for performing a first operation by multiplying the delayed test wave form with the output wave form. The first integrator electrically coupled to the first multiplier for integrating the result of the first operation for a period to generate a first weighted value. The second multiplier for performing a second operation by multiplying the test wave form with the output wave form. The second integrator electrically coupled to the second multiplier for integrating the result of the second operation for the same period to generate a second weighted value.

Abstract: The present invention provides an IC ESD cell, which is applicable to multiple-power-input and mixed-voltage ICs and capable of maintaining power sequence independence of each power source. The ESD cell of the present invention comprises a voltage selector circuit, which connects two separate power sources to select the one having a higher potential as the output voltage. An NMOS is used to connect the two separate power sources. An RC circuit is connected to an output of the voltage selector circuit to distinguish ESD event from normal power source. Therefore, the channel of the NMOS will be conducted to let the ESD current be led out via a designed path, hence preventing internal circuits of an IC from damage and accomplishing the object of whole chip protection.

Abstract: An electrostatic discharge (ESD) protection circuit is disclosed. This invention relates an electrostatic discharge protection circuit for multi-power and mixed-voltage integrated circuit. In the electrostatic discharge protection circuit of the invention, an ESD protection cell formed with voltage selector, control circuit and transistor is used to connect with a independent power and ESD bus is used to connect with each ESD protection cell so that each power is isolated from each other during normal operation. Therefore, each power can be operated independently and circuit will be prevented from ESD during ESD discharging.

Abstract: A method for detecting the speed of a sledge motor in an optical storage device. In response to a track jumping command, a tracking servo output signal is expanded onto an orthogonal space to obtain simulation parameters corresponding to the tracking servo output signal. A pseudo-tracking servo output signal is generated according to the simulation parameters of the tracking servo output signal. Then, the pseudo-tracking servo output signal is used to compute the speed of the sledge motor.

Abstract: A device for compensating the error signal produced by a high-speed disk system. The error signal is fed to a compensator and a bandpass filter respectively. The processed signals produced by the compensator and the bandpass filter are summed to output a compensated signal. The bandpass filter processes the rotating frequency portion of the error signal. The compensator includes a lead compensator and a lag compensator either serially connected or parallel connected.

Abstract: The present invention provides a process for fabricating a self-aligned split gate flash memory. First, a patterned gate oxide layer, a first patterned polysilicon layer, and a first patterned mask layer are successively formed on a semiconductor substrate, and a first insulating spacer is formed on their sidewalls. Then, shallow trench isolation (STI) is formed in the substrate using the first patterned mask layer and the first insulating spacer as a mask. Then, the first patterned mask layer and a part of the first insulating spacer are removed to expose the first patterned polysilicon layer. A floating gate region is defined on the first patterned polysilicon layer, and the surface of the first polysilicon layer in the floating gate region is selectively oxidized to form polysilicon oxide layer. Then, the polysilicon oxide layer is used as a mask to remove the underlying first polysilicon layer in a self-aligned manner to form a floating gate.