Abstract: Over-erase verification and repair methods for a flash memory. The flash memory is an NOR type stack flash. The disclosed method performs an over-erased column verification test on a sector of the NOR type stack flash column by column. An over-erased column repair process is individually performed on the columns which do not pass the over-erased column verification test. For the columns processed by the over-erased column repair process but still incapable of passing the over-erased column verification test, an over-erased bit verification test is performed on each bit thereof. The bits incapable of passing the over-erased bit verification test are further processed by an over-erased repair process individually.

Abstract: A local resistance heating device with a controlled atmosphere, which includes two end members and a mid member, is provided. The two end members are respectively connected with an anode pole and a cathode pole, each end member has an air channel, the air channel of one of the end members is adapted to connect with an output terminal of a gas supplier, and the air channel of the other one of the end members is adapted to connect with a sucking terminal of the gas supplier. The mid member is arranged between the two end members, wherein the two end members and the mid member jointly define a heating room communicating with the air channels of the two end members.

Abstract: An I/O pad ESD protection circuit is composed of a SCR circuit, a first diode, a second diode, and an anti-latch-up circuit. The SCR circuit has a first connection terminal and a second connection terminal, respectively coupled to the I/O pad and the ground voltage, so as to discharge the electrostatic charges. The anti-latch-up circuit has two terminals, which are respectively coupled to the voltage source and the ground voltage, and another connection terminal, used to send an anti-latch-up signal to the SCR for changing the activating rate. The latch-up phenomenon is avoided.

Abstract: The present invention relates to a silicone containing encapsulant composition. One embodiment of the encapsulant composition comprises (a) 30˜60 weight % of an epoxy resin; (b) 30˜60 weight % of an acid anhydride curing agent; (c) 0.1˜30 weight % of a Carbinol function silicone resin which can form a homogeneous mixture with (a) and (b) described above; and (d) 0.1˜5 weight % of a reactive UV absorber or HALS; and reactive anti-oxidant and/or phosphor containing flame retardant. The encapsulant composition can be used for a solid state light emitting device to achieve low internal stress and better -anti-yellowing performance.

Abstract: An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.

Abstract: An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.

Abstract: The present invention relates to a silicone containing encapsulant composition. One embodiment of the encapsulant composition comprises (a) 30˜60 weight % of an epoxy resin; (b) 30˜60 weight % of an acid anhydride curing agent; (c) 0.1˜30 weight % of a Carbinol function silicone resin which can form a homogeneous mixture with (a) and (b) described above; and (d) 0.1˜5 weight % of a reactive UV absorber or HALS; and reactive anti-oxidant and/or phosphor containing flame retardant. The encapsulant composition can be used for a solid state light emitting device to achieve low internal stress and better-anti-yellowing performance.

Abstract: An encryption/decryption method and devices for protecting data in a memory device from unauthorized access is provided. First, obtaining a specific code from a memory device and then encrypting the specific code and original data for obtaining encrypted data during a write cycle. Finally, writing the encrypted data to the memory device according to an access address. The access address can be also encrypted to generate the encrypted data. The encryption level increases by this way so that the valuable information is under protection.

Abstract: An individual flexible tubular packaging bag for sanitary products includes a flexible bag body made from a flexible seamless tubular body of a heat-weldable material by heat-sealing two opposite ends of the seamless tubular body. The flexible bag body defines a receiving space that is adapted to receive the sanitary products, and has an access opening in spatial communication with the receiving space. A resealable flap is connected to the flexible bag body, and seals openably the access opening.

Abstract: In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

Abstract: A digital photo frame with a power saving function includes a time-counting unit, a sensing unit, a displaying unit, and a processing unit. The time-counting unit is used for generating a time-counting signal. The sensing unit is used for sensing the environmental status and generating a sensing signal. The displaying unit is used for displaying an image data. The processing unit controls the sensing unit and the displaying unit. The processing unit further uses a power control unit to control the power supply according to the time-counting signal and the sensing signal so that the digital photo frame operates in a normal mode. After the processing unit does not receive the sensing signal within a pre-determined period counted by the time-counting signal, the processing unit controls the power supply so that the digital photo frame operates in a power saving mode. Hereby, the goal of power saving is achieved.

Abstract: A hemorrhoid pad includes a folded laminated body having a folded end and two opposite folded halves diverging from the folded end. Each of the folded halves of the folded laminated body has inner and outer surfaces. The inner surfaces of the folded halves have a release agent coated thereon and face toward each other.

Abstract: A digital channel generation apparatus is provided for easily setting up a digital channel by a user. The digital channel generation apparatus includes a storage unit, a user interface, and a processing unit. The storage unit stores a plurality of set-top box data, a plurality of electronic device data, a plurality of multimedia data, and at least one channel set-up template. The user interface provides the user a functionality of selecting at least one electronic device data from the plurality of electronic device data. Furthermore, the user interface provides the user a functionality of inputting a set-up data of the digital channel based on the channel set-up template. The processing unit coupled to the user interface generates the digital channel for broadcasting the plurality of multimedia data based on the selected electronic device data, the plurality of set-top box data, the channel set-up template and the set-up data.

Abstract: A digit button-operated air compressor output control structure for controlling output of compressed air from an air compressor by means of a digital control panel and an air pressure regulating structure with internal pressure sensors for enabling the user to set the desired output air pressure quickly and to control the output air pressure stably.

Abstract: A sensing circuit for multi-level flash memory is disclosed. The advantages of the sensing circuit are reducing the circuit size, reducing the testing time for tuning reference voltage and maintaining a constant difference between two approximate reference voltages. The sensing circuit comprises a reference voltage generator which includes a number of serial connected resistive devices and provides several reference voltages by voltage division; a data saving circuit outputs a data voltage; a comparing circuit compares the data voltage with the several reference voltages to output a comparing signal; a decoder receives and then decodes the comparing signal to output the data.

Abstract: An apparatus and method for accessing data from a storage medium is disclosed. The apparatus fetches a data block from the storage medium via an accessing unit, and corrects an error of the data block by an error correction code (ECC) decoder according to an ECC of the data block. The apparatus also includes an error detection code (EDC) processor for calculating an EDC of each data sector of the data block, and a flag register for storing a flag associated with each data sector. The method includes re-fetching a data sector if the associated flag indicates the EDC of the data sector is incorrect; and bypassing a data sector if the associated flag indicates that the EDC of the data sector is correct, even though the ECC of the data block indicates that the data sector contains an error.

Abstract: In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

Abstract: A sensing circuit for multi-level flash memory is disclosed. The advantages of the sensing circuit are reducing the circuit size, reducing the testing time for tuning reference voltage and maintaining a constant difference between two approximate reference voltages. The sensing circuit comprises a reference voltage generator which includes a number of serial connected resistive devices and provides several reference voltages by voltage division; a data saving circuit outputs a data voltage; a comparing circuit compares the data voltage with the several reference voltages to output a comparing signal; a decoder receives and then decodes the comparing signal to output the data.

Abstract: In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

Abstract: An I/O pad ESD protection circuit is composed of a SCR circuit, a first diode, a second diode, and an anti-latch-up circuit. The SCR circuit has a first connection terminal and a second connection terminal, respectively coupled to the I/O pad and the ground voltage, so as to discharge the electrostatic charges. The anti-latch-up circuit has two terminals, which are respectively coupled to the voltage source and the ground voltage, and another connection terminal, used to send an anti-latch-up signal to the SCR for changing the activating rate. The latch-up phenomenon is avoided.