Abstract: An icing detector probe includes three sections arranged sequentially along the direction of air flow, namely, a first section, a second section and a third section. The shape of the outer surface of the first section is suitable for collecting droplets in the air flow. The shape of the outer surface of the second section is suitable for full decelerating and releasing latent heat of large droplets during their movements. The outer surface of the third section is suitable for icing of large droplets. The probe detects icing by distinguishing and identify large droplets icing. The probe effectively detects types of traditional icing, thus being helpful for exact detection of icing thickness. An icing detector including said icing detector probe is also provided.

Abstract: The present invention discloses a network connection method and system. The method includes: grouping a plurality of terminals, allocating group identities, and establishing a mapping relationship between the group identities and terminal identities; establishing a group-based signaling radio bearer and a group-based data radio bearer for each group; allocating, when a terminal in each group access a network, the terminal the group-based signaling radio bearer and group-based data radio bearer corresponding to the group to which the terminal belongs according to a mapping relationship between a group identities and a terminal identity, so that the terminals initiate network access by using the group-based signaling radio bearer and the group-based data radio bearer. The signaling overhead of establishing signaling connection and data bearer may be reduced though the technical solution of the present invention.

Abstract: The present invention provides a method for preparing an ultra-thin material on insulator through adsorption by a doped ultra-thin layer. In the method, first, an ultra-thin doped single crystal film and an ultra-thin top film (or contains a buffer layer) are successively and epitaxially grown on a first substrate, and then a high-quality ultra-thin material on insulator is prepared through ion implantation and a bonding process. A thickness of the prepared ultra-thin material on insulator ranges from 5 nm to 50 nm. In the present invention, the ultra-thin doped single crystal film adsorbs the implanted ion, and a micro crack is then formed, so as to implement ion-cut; therefore, the roughness of a surface of a ion-cut material on insulator is small.

Abstract: There is provided a lighting apparatus and a method for reducing discomfort glare. The method comprises a step of providing a first portion of light radiation in a first incident angle range; and another step of providing a second portion of light radiation in a second incident angle range consecutive to the first incident angle range. The first incident angle range is greater than the second incident angle range viewed from a vertically downward direction of a light source emitting the light radiation, and the correlated color temperature of the first portion of light radiation is lower than that of the second portion of light radiation.

Abstract: A method for measuring a carrier in a deactivated state. The method includes receiving a configuration mode that does not take effect immediately by a user terminal (UE). If a deactivation control signal for a carrier is received by the UE or if a carrier timer of the UE expires, then the method includes switching the carrier from an activated state to a deactivated state, and measuring the carrier in deactivated state by the UE. Alternatively, if an activation control signal for a carrier in the deactivated state that is being measured is received by the UE, the method includes terminating measurement of the carrier in the deactivated state by the UE. Through controllable deactivated carrier measurement, the UE reduces battery power consumption and improves system performance. Embodiments also include an apparatus for measuring a carrier in deactivated state, a base station, and computer-readable storage medium for performing the method.

Abstract: A working tool includes a housing (10) and a lever (3) having a gap defined therein for accommodating a rotatable switch lock (1). The switch lock has a first engagement portion (1a) defined on a first side and a stopper portion (1b) defined on a second side, and the lever has a support portion (3a) proximal to the first engagement portion. A handle portion of the housing has a left push button (8) and a right push button (5) inserted therein, a first groove (8a) and a second groove (8b) of the left push button (8) and right push button (5) each having a second engagement portion formed on a groove wall thereof, each of a first extension section (3a-2) and second extension sections (3a-1) being provided with, at a side facing a corresponding second engagement portion, a third engagement portion engageable with the corresponding second engagement portion.

Abstract: The present invention provides a method for preparing a GOI chip structure, where, in the method, first, a SiGe on insulator (SGOI) chip structure is made by using a SMART CUT technology, and then, germanium condensation technology is performed on the SGOI chip structure, so as to obtain a GOI chip structure. Because the SGOI made by the Smart-Cut technology basically has no misfit dislocation in an SGOI/BOX interface, the threading dislocation density of the GOI is finally reduced. A technique of the present invention is simple, the high-quality GOI chip structure can be implemented, and the germanium condensation technology is greatly improved. An ion implantation technology and an annealing technology are quite mature techniques in the current semiconductor industry, so that such a preparation method greatly improves the possibility of wide use of the germanium concentration technology in the semiconductor industry.

Abstract: A rotary damper with a toothed wheel gear projecting away from a housing having snap-in connection structures disposed on opposing sides of the wheel gear. The wheel gear may be inserted through a panel opening having a pair of opposing transverse slots. In the assembled condition, the housing with the connected wheel gear may slide linearly in the longitudinal direction of the slots to permit self-adjustment relative to an operatively connected mating gear. Proper meshing relation between the wheel gear and the mating gear is thereby maintained.

Abstract: A silicon/germanium (SiGe) heterojunction Tunnel Field Effect Transistor (TFET) and a preparation method thereof are provided, in which a source region of a device is manufactured on a silicon germanium (SiGe) or Ge region, and a drain region of the device is manufactured in a Si region, thereby obtaining a high ON-state current while ensuring a low OFF-state current. Local Ge oxidization and concentration technique is used to implement a Silicon Germanium On Insulator (SGOI) or Germanium On Insulator (GOI) with a high Ge content in some area. In the SGOI or GOI with a high Ge content, the Ge content is controllable from 50% to 100%. In addition, the film thickness is controllable from 5 nm to 20 nm, facilitating the implementation of the device process. During the oxidization and concentration process of the SiGe or Ge and Si, a SiGe heterojunction structure with a gradient Ge content is formed between the SiGe or Ge and Si, thereby eliminating defects.

Abstract: A silicon/germanium (SiGe) heterojunction Tunnel Field Effect Transistor (TFET) and a preparation method thereof are provided, in which a source region of a device is manufactured on a silicon germanium (SiGe) or Ge region, and a drain region of the device is manufactured in a Si region, thereby obtaining a high ON-state current while ensuring a low OFF-state current. Local Ge oxidization and concentration technique is used to implement a Silicon Germanium On Insulator (SGOI) or Germanium On Insulator (GOI) with a high Ge content in some area. In the SGOI or GOI with a high Ge content, the Ge content is controllable from 50% to 100%. In addition, the film thickness is controllable from 5 nm to 20 nm, facilitating the implementation of the device process. During the oxidization and concentration process of the SiGe or Ge and Si, a SiGe heterojunction structure with a gradient Ge content is formed between the SiGe or Ge and Si, thereby eliminating defects.

Abstract: A blower fan including a motor having a rotating shaft, a bracket, a fan housing having a cavity, a fan wheel, and fan blades. The motor is disposed on the fan housing via the bracket. An extended portion of the rotating shaft extends into the cavity of the fan housing and connects with the fan wheel. The fan blades are disposed on the rotating shaft and between the motor and the fan housing. On the casing of the motor is disposed with air vents. The bracket forms an annular side wall. A cavity is formed inside the annular side wall. The annular side wall is outfitted with air outlets which are connected with the cavity of the annular side wall and the fan blades are disposed in the cavity.

Abstract: The instant disclosure provides a push latch having a pivotally mounted blocking hammer including a head with a lever arm extending away from the head to a counter-weight. Under normal operating conditions, the hammer is held in an inert/balanced condition. Under such normal conditions, a portion of the hammer head may be in periodic contact with a resin of tacky character defining a bumper to aid in dampening vibration. Upon the occurrence of a high impact force, the rotational force provided by the counterweight is sufficient to cause the hammer to rotate into blocking relation relative to the latching mechanism so as to prevent unlatching. In the rotated condition, the counterweight may be in contact with an optional resin of tacky character defining a bumper to reduce rebound action.

Abstract: A method of fabricating an isolation structure of a semiconductor device includes the following steps. Firstly, a substrate including a first surface and a second surface is provided. At least one trench is formed in the first surface of the substrate. The trench has a sidewall and a bottom surface. Then, a first chemical vapor deposition process is performed to form a first isolation layer on the first surface of the substrate and the sidewall and the bottom surface of the trench. Then, an anisotropic surface treatment process is performed, so that a surface of the first isolation layer has differential surface chemical properties. Afterwards, a second chemical vapor deposition process is performed to form a second isolation layer on the first isolation layer with a surface having differential surface chemical properties.

Abstract: A method of forming interlayer dielectric comprising the steps of forming a first undoped layer, forming in-situ and sequentially a doped layer and a second undoped layer on the first undoped layer, and planarizing the second undoped layer.

Abstract: A method for forming an edge-chamfered substrate with a buried insulating layer is provided, which comprises the following steps: providing a first substrate (S10); forming an etching mask layer on surfaces of the first substrate, wherein said etching mask layer is formed on the whole surfaces of the first substrate (S11); chamfering a glazed surface of the first substrate and the etching mask layer thereon by the edge grinding (S12); by rotary etching, etching the first substrate which is exposed by the edge grinding on the etching mask layer (S13); providing a second substrate (S14); and bonding the first substrate to the second substrate with a buried insulating layer (S15). The method avoids the edge collapses and the changes of the warp degree in subsequent processes.

Abstract: The present invention provides a method for preparing a GOI chip structure, where, in the method, first, a SiGe on insulator (SGOI) chip structure is made by using a Smart-Cut technology, and then, germanium condensation technology is performed on the SGOI chip structure, so as to obtain a GOI chip structure. Because the SGOI made by the Smart-Cut technology basically has no misfit dislocation in an SGOI/BOX interface, the threading dislocation density of the GOI is finally reduced. A technique of the present invention is simple, the high-quality GOI chip structure can be implemented, and the germanium condensation technology is greatly improved. An ion implantation technology and an annealing technology are quite mature techniques in the current semiconductor industry, so that such a preparation method greatly improves the possibility of wide use of the germanium concentration technology in the semiconductor industry.

Abstract: The present invention discloses a method of fabricating high-mobility dual channel material based on SOI substrate, wherein compressive strained SiGe is epitaxially grown on a conventional SOI substrate to be used as channel material of PMOSFET; Si is then epitaixally grown on SiGe, and approaches such as ion implantation and annealing are employed to allow relaxation of part of strained SiGe and transfer strain to the Si layer thereon so as to form strained Si material as channel material of NMOSFET. With simple process and easy realization, this method can provide high-mobility channel material for NMOSFET and PMOSFET at the same time, well meeting the requirement of simultaneously enhancing the performance of NMOSFET and PMOSFET devices and therefore providing potential channel material for CMOS process of the next generation.

Abstract: A method for preparing a semiconductor substrate with an buried insulating layer by a guttering process, includes the following steps: providing a device substrate and a supporting substrate; forming an insulating layer on a surface of the device substrate; performing a heating treatment on the device substrate, so as to form a denuded zone on the surface of the device substrate; bonding the device substrate having the insulating layer with the supporting substrate, such that the insulating layer is sandwiched between the device substrate and the supporting substrate; annealing and reinforcing a bonding interface, such that an adherence level of the bonding interface meets requirements in the following chamfering grinding, thinning and polishing processes; performing the chamfering grinding, thinning and polishing processes on the device substrate which is bonded.

Abstract: The present invention provides a semiconductor structure with a hybrid of Ge and a group III-V material coplanar and a preparation method thereof. A heterogeneously integrated semiconductor structure with Ge and a group III-V semiconductor material coplanar includes at least one Ge substrate formed on a bulk silicon substrate, and the other substrate is the group III-V semiconductor material formed on the Ge semiconductor.

Abstract: The present invention provides a device system structure based on hybrid orientation SOI and channel stress and a preparation method thereof. According to the preparation method provided in the present invention, first, a (100)/(110) global hybrid orientation SOI structure is prepared; then, after epitaxially growing a relaxed silicon-germanium layer and strained silicon layer sequentially on the global hybrid orientation SOI structure, an (110) epitaxial pattern window is formed; then, after epitaxially growing a (110) silicon layer and a non-relaxed silicon-germanium layer at the (110) epitaxial pattern window, a surface of the patterned hybrid orientation SOI structure is planarized; then, an isolation structure for isolating devices is formed; and finally, a P-type high-voltage device structure is prepared in a (110) substrate portion, an N-type high-voltage device structure and/or low voltage device structures are prepared in the (100) substrate portion.