Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.

Abstract: A method for fabricating a semiconductor device including three-dimensional and planar memory device co-integration includes forming trenches within a horizontal electrode stack to expose portions of a conductive layer, forming vertical electrodes including conductive material within the trenches, forming a planar memory device stack across the device, and patterning the planar memory device stack to form a planar memory device.

Abstract: A method for fabricating an electronic fuse includes forming a recess within a film material to define opposed contact segments and a central fuse segment interconnecting the contact segments and altering the material of the central fuse segment of the film material to increase electrical resistance characteristics of the central fuse segment. The central fuse segment may include defects such as voids created by directing a laser at the central fuse segment as a component of a laser annealing process. Alternatively, and or additionally, the central fuse segment may include dopants implementing via an ion implantation process to increase resistance characteristics of the central fuse segment.

Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.

Abstract: A magnetic random access memory (MRAM) device includes a conductor disposed in an insulating material of a lower wiring layer, a magnetic tunnel junction (MTJ) structure formed in an upper wiring layer, and a landing pad formed in an intermediary wiring layer between the lower and upper wiring layers, the landing pad extending from a top surface of the conductor to a height above the intermediary wiring layer, wherein the landing pad connects the MJT structure to the conductor.

Abstract: A method is presented for reducing dielectric gouging during etching processes of a magnetoresistive random access memory (MRAM) structure including an MRAM region and a non-MRAM region. The method includes forming protective layers in the MRAM region to preserve integrity of underlying dielectric layers, forming a bottom electrode in direct contact with the protective layers, and constructing an MRAM pillar over the bottom electrode, wherein the MRAM pillar includes a magnetic tunnel junction (MTJ) stack and a top electrode.

Abstract: Techniques are provided to fabricate semiconductor devices. For example, a semiconductor device can include an alternating arrangement of vertical metallic lines defining openings therebetween on a substrate. An interlevel dielectric layer is disposed on a consecutive first opening and a second opening to seal an air gap between a top surface of the substrate and a bottom surface of the interlevel dielectric layer.

Abstract: A document including a Directed Self-Assembly (DSA) pattern including a unique and randomized pattern embedded on the document, where the DSA is formed by using two different-length polymer chains.

Abstract: A method of forming magnetic device structures and electrical contacts, including removing a portion of a second interlayer dielectric (ILD) layer to expose an underlying portion of a cap layer in a first device region, wherein the cap layer is on a first ILD layer, while leaving an ILD block in a second device region, forming a spacer layer on the exposed portion of the cap layer in the first device region, forming an electrical contact layer on the spacer layer in the first device region, forming a magnetic device layer on the electrical contact layer and ILD block, removing portions of the magnetic device layer to form a magnetic device stack on the ILD block, and removing portions of the electrical contact layer to form electrical contact pillars, wherein the portions of the electrical contact layer and portions of the magnetic device layer are removed at the same time.

Abstract: An integrated circuit (IC) device, such as a wafer, die, or the like, includes a viscoelastic pad upon a contact. The viscoelastic pad includes a viscoelastic material and an electrically conductive material within the viscoelastic material. The viscoelastic pad provides for a probe needle of an IC device tester to be electrically connected to the IC device contact without the probe needle directly contacting the IC device contact. The viscoelastic pad may be probed multiple instances by the probe needle and may be washed or otherwise removed from the IC device after testing is completed. The viscoelastic pad may be formed upon the IC device by forming the viscoelastic material within a mask, aligning the viscoelastic pad to the IC device contact, and ejecting the viscoelastic material from the mask upon the IC device contact.

Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.

Abstract: Embodiments include method, systems and computer program products for providing medication-related feedback. Aspects include receiving medication information for a patient. Aspects also include receiving a biological, behavioral, or environmental output from a sensor. Aspects also include determining, based upon the biological, behavioral, or environmental output and the medication information for the patient, whether a medication dose is needed. Aspects also include, based on a determination that the medication dose is needed, generating an alert.

Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.

Abstract: Integration of structures including an embedded magnetoresistive random access memory (MRAM) device such as a magnetic tunneling junction device includes pre-patterned etch stop layers to prevent excessive etching of the interlayer dielectric during a via open step.

Abstract: Techniques for preventing switching of spins in a magnetic tunnel junction by stray magnetic fields using a thin film magnetic shield are provided. In one aspect, a method of forming a magnetic tunnel junction includes: forming a stack on a substrate, having a first magnetic layer, a tunnel barrier, and a second magnetic layer; etching the stack to partially pattern the magnetic tunnel junction in the stack, wherein the etching includes patterning the magnetic tunnel junction through the second magnetic layer, the tunnel barrier, and partway through the first magnetic layer; depositing a first spacer and a magnetic shield film onto the partially patterned magnetic tunnel junction; etching back the magnetic shield film and first spacer; complete etching of the magnetic tunnel junction through the first magnetic layer to form a fully patterned magnetic tunnel junction; and depositing a second spacer onto the fully patterned magnetic tunnel junction.

Abstract: Multilayered hardmask structures are provided which can prevent degradation of the performance of a magnetic tunnel junction (MTJ) structure. The multilayered hardmask structures include at least a halogen barrier hardmask layer and an upper hardmask layer. The halogen barrier hardmask layer can prevent halogen ions that are used to pattern the upper hardmask layer from diffusing into the MTJ structure.

Abstract: Embodiments of the invention are directed to a method of forming a memory element pillar. The method includes forming memory element stack layers, forming a conductive cap layer over the memory element stack layers, forming a conductive seal layer over the cap layer, and forming a conductive etch stop layer over the conductive seal layer, wherein the conductive etch stop layer comprises a substantially planar surface. A hardmask is formed over the substantially planar surface of the conductive etch stop layer, wherein the hardmask defines dimensions of the memory element pillar.

Abstract: A substantially flat bottom electrode embedded in a dielectric for magnetoresistive random access memory (MRAM) devices includes pre-filling the contact via prior to filling the trench with tantalum nitride in a via/trench structure. The top surface of the substantially flat bottom electrode is coplanar to the top surface of the dielectric.

Abstract: Integration of structures including an embedded magnetoresistive random access memory (MRAM) device such as a magnetic tunneling junction device includes pre-patterned etch stop layers to prevent excessive etching of the interlayer dielectric during a via open step.

Abstract: Techniques are provided for fabricating magnetic random-access memory devices, which eliminate junction shorts and minimize gouging of an underlying insulating layer. For example, a bottom electrode layer, a magnetic tunnel junction (MTJ) stack, and an upper electrode layer are formed over an insulating layer. The bottom electrode layer and the MTJ stack are etched to form an upper electrode and a MTJ structure. A cleaning etch process removes residual metallic material which is re-deposited on sidewalls of the MTJ structure as a result of etching the MTJ stack. A conformal dielectric layer is formed to encapsulate the upper electrode and the MTJ structure and prevent oxidation or re-deposition of metallic material on the cleaned sidewalls of the MTJ structure. A final etch process is performed to pattern the conformal dielectric layer and bottom electrode layer to form a spacer on sidewalls of the MTJ structure and form a bottom electrode.