Patents by Inventor Michael RIZZOLO

Michael RIZZOLO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9881431
    Abstract: An aspect of the disclosure includes a security system and method having a key with nanoscale features. The key includes a body. At least one pattern member disposed on the body, the pattern member formed using a directed self-assembly polymer to define a pattern of random feature structures thereon, the feature structures having a width of less than 100 nanometers.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: January 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Michael Rizzolo
  • Publication number: 20180005883
    Abstract: A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Benjamin David BRIGGS, Lawrence A. CLEVENGER, Bartlet H. DEPROSPO, Michael RIZZOLO
  • Publication number: 20180005937
    Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Benjamin David Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Michael Rizzolo, Nicole Adelle Saulnier
  • Publication number: 20180005941
    Abstract: A semiconductor device includes a porous dielectric layer formed on an interconnect layer and including a recessed portion, a conductive layer formed in the recessed portion, and a conformal cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the conformal cap layer. Porous dielectric material is protected by back-filled pore fillers or leave-in porogens from process integration such as chemical mechanical polishing (CMP). The pore fillers or porogens are removed after CMP and Cap process to achieve low capacitance. A self-aligned cap protects the conductor metal from exposing the severe conditions during the pore filler or porogen removal process.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Benjamin David BRIGGS, Lawrence A. CLEVENGER, Bartlet H. DEPROSPO, Huai HUANG, Christopher J. PENNY, Michael RIZZOLO
  • Publication number: 20180005953
    Abstract: A method of fabricating a metallization layer of a semiconductor device in which copper is used for an interconnect material and cobalt is used to encapsulate the copper. A material is introduced that will interact with the cobalt to cause a hexagonal-close-packed (HCP) crystal structure of cobalt to change to a face-centered-cubic (FCC) crystal structure of cobalt, the FCC crystal structure providing a resistance of the cobalt to migrate.
    Type: Application
    Filed: August 14, 2017
    Publication date: January 4, 2018
    Inventors: Benjamin D. Briggs, James J. Kelly, Koichi Motoyama, Roger Allan Quon, Michael Rizzolo, Theodorus Eduardus Standaert
  • Publication number: 20180005880
    Abstract: A method of forming a semiconductor structure includes forming at least one trench in a dielectric layer, forming a barrier layer on a bottom of said at least one trench, sidewalls of said at least one trench and a top surface of the dielectric layer, the barrier layer having a non-uniform thickness, and selectively thinning at least a first portion of the barrier layer using one or more cycles comprising forming an oxidized layer in the first portion of the barrier layer using a neutral beam oxidation and removing the oxidized layer using an etching process.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Cornelius Brown Peethala, Michael Rizzolo, Chih-Chao Yang
  • Publication number: 20180005868
    Abstract: A conductive line structure comprises a first conductive line arranged in a first dielectric layer, a second conductive line arranged in the first dielectric layer, a cap layer arranged on the first conductive line and the second conductive line, and an airgap arranged between the first conductive line and the second conductive line, the airgap defined by the first dielectric layer and the cap layer.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Patent number: 9858388
    Abstract: A system for monitoring participants in a group includes one or more thermal image capturing devices configured to capture one or more thermal images of a plurality of participants in an event, and a processing device configured to receive the one or more thermal images and identification data for at least one of the plurality of participants. The processing device is configured to perform a method that includes identifying the at least one of the plurality of participants, calculating a heat profile of the at least one of the plurality of participants, comparing the heat profile to a reference profile, and determining whether a deviation exists between the heat profile and the reference profile. The method also includes, based on detecting the deviation, calculating a magnitude of the deviation and determining whether a health risk exists based on the magnitude of the deviation.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maryam Ashoori, Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Jonathan H. Connell, II, Nalini K. Ratha, Michael Rizzolo
  • Publication number: 20170368992
    Abstract: Techniques are provided for alerting drivers of hazardous driving conditions using the sensing capabilities of wearable mobile technology. In one aspect, a method for alerting drivers of hazardous driving conditions includes the steps of: collecting real-time data from a driver of a vehicle, wherein the data is collected via a mobile device worn by the driver; determining whether the real-time data indicates that a hazardous driving condition exists; providing feedback to the driver if the real-time data indicates that a hazardous driving condition exists, and continuing to collect data from the driver in real-time if the real-time data indicates that a hazardous driving condition does not exist. The real-time data may also be collected and used to learn characteristics of the driver. These characteristics can be compared with the data being collected to help determine, in real-time, whether the driving behavior is normal and whether a hazardous driving condition exists.
    Type: Application
    Filed: August 21, 2017
    Publication date: December 28, 2017
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Jonathan H. Connell, II, Nalini K. Ratha, Michael Rizzolo
  • Publication number: 20170368991
    Abstract: Techniques are provided for alerting drivers of hazardous driving conditions using the sensing capabilities of wearable mobile technology. In one aspect, a method for alerting drivers of hazardous driving conditions includes the steps of: collecting real-time data from a driver of a vehicle, wherein the data is collected via a mobile device worn by the driver; determining whether the real-time data indicates that a hazardous driving condition exists; providing feedback to the driver if the real-time data indicates that a hazardous driving condition exists, and continuing to collect data from the driver in real-time if the real-time data indicates that a hazardous driving condition does not exist. The real-time data may also be collected and used to learn characteristics of the driver. These characteristics can be compared with the data being collected to help determine, in real-time, whether the driving behavior is normal and whether a hazardous driving condition exists.
    Type: Application
    Filed: August 21, 2017
    Publication date: December 28, 2017
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Jonathan H. Connell, II, Nalini K. Ratha, Michael Rizzolo
  • Publication number: 20170361201
    Abstract: Embodiments are directed to a support apparatus. The support apparatus might comprise a body configured to support an entity. The body might comprise a material that has a physical property. The support apparatus might further comprise a coupler system configured to couple electric current from a power source to the material. The material is arranged such that coupling an electric current to the material changes the physical property of the material. Embodiments are further directed to a method. The method might comprise forming one or more cavities in a support apparatus. The method might further comprise providing one or more couplers in electrical contact with each of the one or more channels. The method further comprises filling each of the one or more cavities with a fluid that has electrically changeable rigidity. Finally, the method might comprise connecting a power source to each of the one or more couplers.
    Type: Application
    Filed: June 20, 2016
    Publication date: December 21, 2017
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Michael Rizzolo
  • Publication number: 20170358533
    Abstract: Low-temperature techniques for doping of Cu interconnects based on interfacially-assisted thermal diffusion are provided. In one aspect, a method of forming doped copper interconnects includes the steps of: patterning at least one trench in a dielectric material; forming a barrier layer lining the trench; forming a metal liner on the barrier layer; depositing a seed layer on the metal liner; plating a Cu fill into the trench to form Cu interconnects; removing a portion of a Cu overburden to access an interface between the metal liner and the Cu fill; depositing a dopant layer; and diffusing a dopant(s) from the dopant layer along the interface to form a Cu interconnect doping layer between the metal liner and the Cu fill. Alternatively, the overburden and the barrier layer/metal liner can be completely removed, and the dopant layer deposited selectively on the Cu fill. An interconnect structure is also provided.
    Type: Application
    Filed: August 7, 2017
    Publication date: December 14, 2017
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Chao-Kun Hu, Takeshi Nogami, Deepika Priyadarshini, Michael Rizzolo
  • Patent number: 9837355
    Abstract: A method of forming an interconnect to an electrical device is provided. The structure produced by the method may include a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parrallel lengths; and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: December 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
  • Patent number: 9837305
    Abstract: A semiconductor structure that includes: a semiconductor substrate having a semiconductor base and back end of the line (BEOL) wiring layers; a dielectric cap layer on the semiconductor base; trenches on the dielectric cap layer, each of the trenches including dielectric walls, a dielectric bottom in contact with the dielectric cap layer and a metal filling a space between the dielectric walls; air gap openings on the dielectric cap layer and interspersed with the trenches, each air gap opening between the dielectric wall from one metal trench and adjacent to the dielectric wall of a second metal, the dielectric cap layer forming a bottom of the air gap openings; and a second dielectric cap layer formed over the trenches and over the air gap openings, the second dielectric cap layer pinching off each air gap opening.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: December 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Patent number: 9837485
    Abstract: Capacitors and methods of forming the same include forming a gap in a dielectric layer underneath one or more conducting lines, such that the one or more conducting lines are suspended over the gap. A capacitor stack is deposited in the gap and on the conducting lines. Respective contacts are deposited on the conducting lines and on the capacitor stack.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: December 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Publication number: 20170344722
    Abstract: A cognitive health management method, system, and non-transitory computer readable medium, include analyzing user input data of a first user by comparing the user input data of the first user to medical data in the database, and providing both of: a recommendation to the first user based on the comparison of the user input data of the first user to the medical data of the database, and a result feedback including a conclusion of the analyzing to a result feedback section of the database.
    Type: Application
    Filed: May 27, 2016
    Publication date: November 30, 2017
    Inventors: Maryam Ashoori, Benjamin David Briggs, Lawrence A. Clevenger, Leigh Anne Hodges Clevenger, Jonathan Hudson Connell, II, Michael Rizzolo
  • Patent number: 9824982
    Abstract: Methods for enhancing mechanical strength of back-end-of-line (BEOL) dielectrics to prevent crack propagation within interconnect stacks are provided. After forming interconnect structures in a dielectric material layer, a pore filling material is introduced into pores of a portion of the dielectric material layer that is located in a crack stop region present around a periphery of a chip region. By filling the pores of the portion of the dielectric material layer located in the crack stop region, the mechanical strength of the dielectric material layer is selectively enhanced in the crack stop region.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: November 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Publication number: 20170317025
    Abstract: A method of forming an interconnect to an electrical device is provided. The structure produced by the method may include a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parrallel lengths; and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines.
    Type: Application
    Filed: July 14, 2017
    Publication date: November 2, 2017
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
  • Publication number: 20170301621
    Abstract: A method for via alignment includes forming first airgaps between interconnect structures and depositing a pinch off layer to close off openings to the first airgaps. A protection layer is formed in divots in the pinch off layer. The protection layer and the pinch off layer are planarized to form a surface where the protection layer remains in the divots. An interlevel dielectric layer (ILD) is deposited on the surface. The ILD and the pinch off layer are etched using the protection layer as an etch stop to align a via and expose the interconnect structure through the via.
    Type: Application
    Filed: October 28, 2016
    Publication date: October 19, 2017
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
  • Publication number: 20170301749
    Abstract: Capacitors and methods of forming the same include forming a gap in a dielectric layer underneath one or more conducting lines, such that the one or more conducting lines are suspended over the gap. A capacitor stack is deposited in the gap and on the conducting lines. Respective contacts are deposited on the conducting lines and on the capacitor stack.
    Type: Application
    Filed: June 30, 2017
    Publication date: October 19, 2017
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo