Abstract: A thermal interface material and systems and methods for forming a thermal interface material include depositing a layer of a composite material, including at least a first material and a second material, the first material including a carrier fluid and the second material including a filler particle suspended within the first material. A particle manipulator is positioned over the layer of the composite material, the particle manipulator including at least one emitter to apply a particle manipulating field to bias a movement of the filler particles. The second material is redistributed by applying the particle manipulating field to interact with the second material causing the second material to migrate from a surrounding region in the composite material into a high concentration region in the composite material to form a customized thermal interface such that the high concentration region is configured and positioned corresponding to a hotspot.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of memory elements on a first interconnect level, and forming an etch stop layer on the plurality of memory elements. A dielectric layer is formed on the etch stop layer, and a portion of the dielectric over the plurality of memory elements is removed to expose a portion of the etch stop layer. The method further includes removing the exposed portion of the etch stop layer. The removing of the portion of the dielectric layer and of the exposed portion of the etch stop layer forms a trench. A metallization layer is formed in the trench on the plurality of memory elements, wherein the metallization layer is part of a second interconnect level.

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer surrounding contacts over a top surface and bevel edge of a substrate, forming a sacrificial buffer layer over the dielectric layer, removing portions of the sacrificial buffer layer formed over the dielectric layer on the top surface of the substrate, and patterning device structures including one or more metal layers over the contacts, wherein patterning the device structures removes portions of the metal layers formed over the top surface of the substrate leaving the metal layers on the bevel edge. The method also includes forming an encapsulation layer and performing a bevel dry etch to remove the encapsulation layer and the metal layers on the bevel edge. The bevel dry etch damages the sacrificial buffer layer on the bevel edge underneath the metal layers. The method further includes removing the damaged sacrificial buffer layer from the bevel edge.

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer surrounding contacts over a top surface and bevel edge of a substrate, forming a sacrificial buffer layer over the dielectric layer, removing portions of the sacrificial buffer layer formed over the dielectric layer on the top surface of the substrate, and patterning device structures including one or more metal layers over the contacts, wherein patterning the device structures removes portions of the metal layers formed over the top surface of the substrate leaving the metal layers on the bevel edge. The method also includes forming an encapsulation layer and performing a bevel dry etch to remove the encapsulation layer and the metal layers on the bevel edge. The bevel dry etch damages the sacrificial buffer layer on the bevel edge underneath the metal layers. The method further includes removing the damaged sacrificial buffer layer from the bevel edge.

Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Abstract: A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

Abstract: A substantially flat bottom electrode embedded in a dielectric for magnetoresistive random access memory (MRAM) devices includes pre-filling the contact via prior to filling the trench with tantalum nitride in a via/trench structure. The top surface of the substantially flat bottom electrode is coplanar to the top surface of the dielectric.

Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including at least a hardmask having a first layer and a second layer, the second layer being a ruthenium layer, and removing the first layer of dual layer hardmask during a via opening such that the ruthenium layer remains intact to protect the RRAM stack during a damascene process.

Abstract: A semiconductor device includes a device magnetic tunnel junction (MTJ) and sensor MTJs. A spin polarization of a free layer of the device MTJ is configurable based at least in part on electrical energy supplied to the device MTJ. A spin polarization of a corresponding free layer of each sensor MTJ is configurable based at least in part on a magnetic field created by the spin polarization of the free layer of the device MTJ. A circuit disposed is in electrical communication with the plurality of sensor MTJs and configured to determine the corresponding free layer spin polarizations of each of the sensor MTJs based at least in part on electrical energy supplied to the sensor MTJs by the circuit. The circuit is configured to determine a magnetoresistance of the device MTJ based at least in part on the determined corresponding free layer spin polarizations of the sensor MTJ.

Abstract: A method for fabricating a semiconductor device including three-dimensional and planar memory device co-integration includes forming trenches within a horizontal electrode stack to expose portions of a conductive layer, forming vertical electrodes including conductive material within the trenches, forming a planar memory device stack across the device, and patterning the planar memory device stack to form a planar memory device.

Abstract: Back end of line (BEOL) metallization structures and methods generally includes forming a landing pad on an interconnect structure. A multilayer structure including layers of metals and at least one insulating layer are provided on the structure and completely cover the landing pad. The landing pad is a metal-filled via and has a width dimension that is smaller than the multilayer structure, or the multilayer structure and the underlying metal conductor in the interconnect structure. The landing pad metal-filled via can have a width dimension that is sub-lithographic.

Abstract: Context appropriate errors are injected into conversational text generated by conversational agents. The conversational agent creates an imperfect conversational text containing at least one text entry error added to the original conversational text. A confidence level that at least one of context and meaning of the imperfect conversational text is consistent with the context and meaning of the original conversational text is determined, and the imperfect conversational text is communicated to a human recipient if the confidence level is above a pre-defined threshold.

Abstract: A method of forming magnetic device structures and electrical contacts, including removing a portion of a second interlayer dielectric (ILD) layer to expose an underlying portion of a cap layer in a first device region, wherein the cap layer is on a first ILD layer, while leaving an ILD block in a second device region, forming a spacer layer on the exposed portion of the cap layer in the first device region, forming an electrical contact layer on the spacer layer in the first device region, forming a magnetic device layer on the electrical contact layer and ILD block, removing portions of the magnetic device layer to form a magnetic device stack on the ILD block, and removing portions of the electrical contact layer to form electrical contact pillars, wherein the portions of the electrical contact layer and portions of the magnetic device layer are removed at the same time.

Abstract: Semiconductor devices including bamboo tall via interconnect structures and methods of forming the bamboo tall via interconnect structures generally include a first via in a first dielectric layer including a liner layer and a bulk conductor in the first via, wherein the bulk conductor includes a recess filled with a conductive metal different from the bulk conductor and selected to prevent diffusion of the bulk conductor. At least one additional via is in a second dielectric layer including a liner layer and a bulk conductor in the least one additional via, wherein the second dielectric layer is on the first dielectric layer, and wherein the bulk conductor includes a recess filled with a conductive metal different from the bulk conductor and selected to prevent diffusion of the bulk conductor. The at least one additional via is aligned with the first via.

Abstract: A method for manufacturing a semiconductor device includes forming one or more memory device layers over a contact structure. In the method, a plurality of hardmask layers are deposited on the one or more memory device layers in a stacked configuration. Alternating hardmask layers of the stacked configuration are different from each other in at least one respect. The method further includes patterning the plurality of hardmask layers and the one or more memory device layers into a pillar over the contact structure.

Abstract: An electrical device structure including a magnetic tunnel junction structure having a first tunnel junction dielectric layer positioned between a free magnetization layer and a fixed magnetization layer. A magnetization enhancement stack present on the magnetic tunnel junction structure. The magnetization enhancement stack includes a second tunnel junction layer that is in contact with the free magnetization layer of the magnetic tunnel junction structure, a metal contact layer present on the second tunnel junction layer, and a metal electrode layer present on the metal contact layer. A metallic ring on a sidewall of the magnetic enhancement stack, wherein a base of the metallic ring may be in contact with the free magnetization layer of the magnetic tunnel junction structure.

Abstract: Techniques are provided to fabricate semiconductor devices. For example, a semiconductor device can include an alternating arrangement of vertical metallic lines defining openings therebetween on a substrate. An interlevel dielectric layer is disposed on a consecutive first opening and a second opening to seal an air gap between a top surface of the substrate and a bottom surface of the interlevel dielectric layer.

Abstract: A semiconductor device that includes a semiconductor substrate having a surface, the surface having several regions having different thermal and/or mechanical requirements; and a composite thermal interface material including several spatially localized thermal interface materials placed on the surface, each of the several thermal interface materials tailored to the different thermal and/or mechanical requirements of each of the regions. Also disclosed is a method of forming the composite thermal interface material.

Abstract: A conductive line structure comprises a first conductive line arranged in a first dielectric layer, a second conductive line arranged in the first dielectric layer, a cap layer arranged on the first conductive line and the second conductive line, and an airgap arranged between the first conductive line and the second conductive line, the airgap defined by the first dielectric layer and the cap layer.

Abstract: A computer-implemented method for calibrating audio of a virtual reality device, the method comprising: determining a difference between a perceived tone location and an actual audible tone location, in response to an emitting of the actual audible tone; wherein the tone comprises a spectral tone, and creating and calibrating a user ear model by: emitting the spectral tone at a random time during a simulation by the virtual reality device; determining the perceived tone location during the simulation; and computing an error adjustment for one or more geometric variables of a default ear model based on a result of the determining.