Patents by Inventor Michal Danek

Michal Danek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11069535
    Abstract: Methods of depositing tungsten into high aspect ratio features using a dep-etch-dep process integrating various deposition techniques with alternating pulses of surface modification and removal during etch are provided herein.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: July 20, 2021
    Assignee: Lam Research Corporation
    Inventors: Chiukin Steven Lai, Keren Jacobs Kanarik, Samantha Tan, Anand Chandrashekar, Teh-Tien Su, Wenbing Yang, Michael Wood, Michal Danek
  • Patent number: 10977405
    Abstract: Provided herein are systems and methods for optimizing feature fill processes. The feature fill optimization systems and methods may be used to optimize feature fill from a small number of patterned wafer tests. The systems and methods may be used for optimizing enhanced feature fill processes including those that include inhibition and/or etch operations along with deposition operations. Results from experiments may be used to calibrate a feature scale behavioral model. Once calibrated, parameter space may be iteratively explored to optimize the process.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: April 13, 2021
    Assignee: Lam Research Corporation
    Inventors: Michael Bowes, Atashi Basu, Kapil Sawlani, Dongyao Li, Anand Chandrashekar, David M. Fried, Michal Danek
  • Patent number: 10916434
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. The methods include performing multi-stage inhibition treatments including intervals between stages. One or more of plasma source power, substrate bias power, or treatment gas flow may be reduced or turned off during an interval. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: February 9, 2021
    Assignee: Lam Research Corporation
    Inventors: Deqi Wang, Anand Chandrashekar, Raashina Humayun, Michal Danek
  • Patent number: 10895539
    Abstract: A system includes a camera mounted external to and adjacent to a window of a processing chamber configured to process semiconductor substrates. The window allows the camera to view a component in the processing chamber. The camera is configured to generate a video signal indicative of a status of the component during a process being performed in the processing chamber. The system further includes a controller coupled to the processing chamber. The controller is configured to control the camera, process the video signal from the camera, determine the status of the component based on the processing of the video signal, and determine whether to terminate the process based on the status of the component.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: January 19, 2021
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Kapil Sawlani, Gary B. Lind, Michal Danek, Ronald Powell, Michael Rumer, Kaihan Ashtiani
  • Publication number: 20200407842
    Abstract: A method includes arranging a substrate in a processing chamber, and exposing the substrate to a gas mixture including a first metal precursor gas and a second metal precursor gas to deposit a first metal precursor and a second metal precursor onto the substrate at the same time. The method further includes purging the processing chamber, supplying a reactant common to both the first metal precursor and the second metal precursor to form a layer of an alloy on the substrate, and purging the processing chamber.
    Type: Application
    Filed: December 6, 2018
    Publication date: December 31, 2020
    Inventors: Ilanit FISHER, Raashina HUMAYUN, Michal DANEK, Patrick VAN CLEEMPUT, Shruti THOMBARE
  • Publication number: 20200402846
    Abstract: Provided herein are methods and apparatuses for forming metal films such as tungsten (W) and molybdenum (Mo) films on semiconductor substrates. The methods involve forming a reducing agent layer, then exposing the reducing agent layer to a metal precursor to convert the reducing agent layer to a layer of the metal. In some embodiments, the reducing agent layer is a silicon- (Si-) and boron- (B-) containing layer. The methods may involve forming the reducing agent layer at a first substrate temperature, raising the substrate temperature to a second substrate temperature, and then exposing the reducing agent layer to the metal precursor at the second substrate temperature. The methods may be used to form fluorine-free tungsten or molybdenum films in certain embodiments. Apparatuses to perform the methods are also provided.
    Type: Application
    Filed: November 19, 2018
    Publication date: December 24, 2020
    Applicant: Lam Research Corporation
    Inventors: Joshua Collins, Griffin John Kennedy, Hanna Bamnolker, Michal Danek, Shruti Vivek Thombare, Patrick van Cleemput, Gorun Butail
  • Publication number: 20200365456
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 19, 2020
    Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick van Cleemput
  • Patent number: 10777453
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: September 15, 2020
    Assignee: Lam Research Corporation
    Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
  • Publication number: 20200286743
    Abstract: Methods of depositing tungsten into high aspect ratio features using a dep-etch-dep process integrating various deposition techniques with alternating pulses of surface modification and removal during etch are provided herein.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: Chiukin Steven Lai, Keren Jacobs Kanarik, Samantha Tan, Anand Chandrashekar, Teh-Tien Su, Wenbing Yang, Michael Wood, Michal Danek
  • Patent number: 10731250
    Abstract: In some embodiments, deposition processes for ruthenium (Ru) feature fill include deposition of a thin, protective Ru film under reducing conditions, followed by a Ru fill step under oxidizing conditions. The presence of protective Ru films formed under oxygen-free conditions or with an oxygen-removing operation can enable Ru fill without oxidation of an underlying adhesion layer or metal feature.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: August 4, 2020
    Assignee: Lam Research Corporation
    Inventors: Do Young Kim, Jeong-Seok Na, Chiukin Steven Lai, Raashina Humayun, Michal Danek
  • Publication number: 20200242209
    Abstract: Provided herein are systems and methods for optimizing feature fill processes. The feature fill optimization systems and methods may be used to optimize feature fill from a small number of patterned wafer tests. The systems and methods may be used for optimizing enhanced feature fill processes including those that include inhibition and/or etch operations along with deposition operations. Results from experiments may be used to calibrate a feature scale behavioral model. Once calibrated, parameter space may be iteratively explored to optimize the process.
    Type: Application
    Filed: January 29, 2019
    Publication date: July 30, 2020
    Inventors: Michael Bowes, Atashi Basu, Kapil Sawlani, Dongyao Li, Anand Chandrashekar, David M. Fried, Michal Danek
  • Publication number: 20200226742
    Abstract: Defects on a substrate comprising electronic components can be classified with a computational defect analysis system that may be implemented in multiple stages. For example, a first stage classification engine may process metrology data to produce an initial classification of defects. A second stage classification engine may use the initial classification, along with manufacturing information and/or prior defect knowledge to output probabilities that the defects are caused by one or more potential sources.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 16, 2020
    Inventors: Kapil Sawlani, Richard A. Gottscho, Michal Danek, Keith Wells, Keith Hansen
  • Publication number: 20200211853
    Abstract: Disclosed are methods of depositing a transition metal such as tungsten on a semiconductor substrate. The method includes providing a gas mixture of diborane with a balance of hydrogen, where the hydrogen serves to stabilize the diborane in the gas mixture. The method further includes delivering the gas mixture to the semiconductor substrate to form a boron layer, where the boron layer serves as a reducing agent layer to convert a metal-containing precursor to metal, such as a tungsten-containing precursor to tungsten. In some implementations, the semiconductor substrate includes a vertical structure, such as a three-dimensional vertical NAND structure, with horizontal features or wordlines having openings in sidewalls of the vertical structure, where the boron layer may be conformally deposited in the horizontal features of the vertical structure.
    Type: Application
    Filed: August 10, 2018
    Publication date: July 2, 2020
    Inventors: Lawrence Schloss, Raashina Humayun, Sanjay Gopinath, Juwen Gao, Michal Danek, Kaihan Abidi Ashtiani
  • Publication number: 20200185273
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Publication number: 20200185225
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. The methods include performing multi-stage inhibition treatments including intervals between stages. One or more of plasma source power, substrate bias power, or treatment gas flow may be reduced or turned off during an interval. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
    Type: Application
    Filed: February 10, 2020
    Publication date: June 11, 2020
    Inventors: Deqi Wang, Anand Chandrashekar, Raashina Humayun, Michal Danek
  • Publication number: 20200144066
    Abstract: Provided herein are methods and apparatuses for reducing line bending when depositing a metal such as tungsten, molybdenum, ruthenium, or cobalt into features on substrates by periodically exposing the feature to nitrogen, oxygen, or ammonia during atomic layer deposition, chemical vapor deposition, or sequential chemical vapor deposition to reduce interactions between metal deposited onto sidewalls of a feature. Methods are suitable for deposition into V-shaped features.
    Type: Application
    Filed: December 21, 2019
    Publication date: May 7, 2020
    Inventors: Adam Jandl, Sema Ermez, Lawrence Schloss, Sanjay Gopinath, Michal Danek, Siew Neo, Joshua Collins, Hanna Bamnolker
  • Publication number: 20200075403
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Application
    Filed: November 6, 2019
    Publication date: March 5, 2020
    Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
  • Patent number: 10580654
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. The methods include performing multi-stage inhibition treatments including intervals between stages. One or more of plasma source power, substrate bias power, or treatment gas flow may be reduced or turned off during an interval. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: March 3, 2020
    Assignee: Lam Research Corporation
    Inventors: Deqi Wang, Anand Chandrashekar, Raashina Humayun, Michal Danek
  • Patent number: 10580695
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: March 3, 2020
    Assignee: Lam Research Corporation
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Patent number: 10573522
    Abstract: Provided herein are methods and apparatuses for reducing line bending when depositing a metal such as tungsten, molybdenum, ruthenium, or cobalt into features on substrates by periodically exposing the feature to nitrogen, oxygen, or ammonia during atomic layer deposition, chemical vapor deposition, or sequential chemical vapor deposition to reduce interactions between metal deposited onto sidewalls of a feature. Methods are suitable for deposition into V-shaped features.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: February 25, 2020
    Assignee: Lam Research Corporation
    Inventors: Adam Jandl, Sema Ermez, Lawrence Schloss, Sanjay Gopinath, Michal Danek, Siew Neo, Joshua Collins, Hanna Bamnolker