Patents by Inventor Michal Danek

Michal Danek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10256142
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: April 9, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Publication number: 20190080914
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. The methods include performing multi-stage inhibition treatments including intervals between stages. One or more of plasma source power, substrate bias power, or treatment gas flow may be reduced or turned off during an interval. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
    Type: Application
    Filed: November 13, 2018
    Publication date: March 14, 2019
    Inventors: Deqi Wang, Anand Chandrashekar, Raashina Humayun, Michal Danek
  • Publication number: 20190019725
    Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
    Type: Application
    Filed: September 6, 2018
    Publication date: January 17, 2019
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Patent number: 10170320
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. The methods include performing multi-stage inhibition treatments including intervals between stages. One or more of plasma source power, substrate bias power, or treatment gas flow may be reduced or turned off during an interval. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: January 1, 2019
    Assignee: Lam Research Corporation
    Inventors: Deqi Wang, Anand Chandrashekar, Raashina Humayun, Michal Danek
  • Publication number: 20180347041
    Abstract: Provided are deposition processes for ruthenium (Ru) feature fill. In some embodiments, the processes include deposition of a thin, protective Ru film under reducing conditions, followed by a Ru fill step under oxidizing conditions. The presence of protective Ru films formed under oxygen-free conditions or with an oxygen-removing operation can enable Ru fill without oxidation of an underlying adhesion layer or metal feature.
    Type: Application
    Filed: June 4, 2018
    Publication date: December 6, 2018
    Inventors: Do Young Kim, Jeong-Seok Na, Chiukin Steven Lai, Raashina Humayun, Michal Danek
  • Patent number: 10128116
    Abstract: Efficient integrated sequential deposition of alternating layers of dielectric and conductor, for example oxide/metal or metal nitride, e.g., SiO2/TiN, in a single tool, and even in a single process chamber enhances throughput without compromising quality when directly depositing a OMOM stack with many layers. Conductor and dielectric film deposition of a stack of at least 20 conductor/dielectric film pairs in the same processing tool or chamber, without breaking vacuum between the film depositions, such that there is no substantial cross-contamination between the conductor and dielectric film depositions, can be achieved.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: November 13, 2018
    Assignee: LAM RESEARCH CORPORATION
    Inventors: William T. Lee, Bart J. van Schravendijk, David Charles Smith, Michal Danek, Patrick A. Van Cleemput, Ramesh Chandrasekharan
  • Patent number: 10103058
    Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 16, 2018
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Publication number: 20180294187
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Application
    Filed: April 9, 2018
    Publication date: October 11, 2018
    Inventors: Shruti Vivek Thombare, Raashina Humayun, Michal Danek, Chiukin Steven Lai, Joshua Collins, Hanna Bamnolker, Griffin John Kennedy, Gorun Butail, Patrick A. van Cleemput
  • Patent number: 10087523
    Abstract: A vaporizer system is provided that allows for rapid shifts in the flow rate of a vaporized reactant while maintaining a constant overall flow rate of vaporized reactant and carrier gas.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: October 2, 2018
    Assignee: Lam Research Corporation
    Inventors: Joshua Collins, Eric H. Lenz, Michal Danek
  • Publication number: 20180277431
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
    Type: Application
    Filed: May 29, 2018
    Publication date: September 27, 2018
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Publication number: 20180240682
    Abstract: Methods of depositing tungsten into high aspect ratio features using a dep-etch-dep process integrating various deposition techniques with alternating pulses of surface modification and removal during etch are provided herein. Methods involve introducing an activation gas at a chamber pressure and/or applying a bias using a bias power selected to preferentially etch the metal at or near the opening of the feature relative to the interior region of the feature. Apparatuses include integrated hardware for performing deposition of metal and atomic layer etching of metal in the same tool and/or without breaking vacuum.
    Type: Application
    Filed: April 16, 2018
    Publication date: August 23, 2018
    Inventors: Chiukin Steven Lai, Keren Jacobs Kanarik, Samantha Tan, Anand Chandrashekar, Teh-tien Su, Wenbing Yang, Michael Wood, Michal Danek
  • Publication number: 20180240675
    Abstract: Methods of depositing fluorine-free tungsten by sequential CVD pulses, such as by alternately pulsing a fluorine-free tungsten precursor and hydrogen in cycles of temporally separated pulses, are provided. Some methods involve depositing fluorine-free tungsten by sequential CVD without depositing a tungsten nucleation layer. Methods also include depositing tungsten directly on a substrate surface using alternating pulses of a chlorine-containing tungsten precursor and hydrogen without treating the substrate surface. Methods also include depositing a tungsten layer using a reducing agent and fluorine-free tungsten-containing precursor and depositing bulk tungsten in sequential CVD cycles of alternating pulses of hydrogen and a tungsten-containing precursor.
    Type: Application
    Filed: April 20, 2018
    Publication date: August 23, 2018
    Inventors: Hanna Bamnolker, Joshua Collins, Tomas Sadilek, Hyeong Seop Shin, Xiaolan Ba, Raashina Humayun, Michal Danek, Lawrence Schloss
  • Publication number: 20180219014
    Abstract: Disclosed herein are methods and related apparatus for formation of multi-component tungsten-containing films including multi-component tungsten-containing films diffusion barriers. According to various embodiments, the methods involve deposition of multi-component tungsten-containing films using tungsten chloride (WClx) precursors and boron (B)-containing, silicon (Si)-containing or germanium (Ge)-containing reducing agents.
    Type: Application
    Filed: March 19, 2018
    Publication date: August 2, 2018
    Inventors: Michal Danek, Hanna Bamnolker, Raashina Humayun, Juwen Gao
  • Patent number: 9997405
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 12, 2018
    Assignee: Lam Research Corporation
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Patent number: 9978605
    Abstract: Provided herein are methods of depositing fluorine-free tungsten by sequential CVD pulses, such as by alternately pulsing a chlorine-containing tungsten precursor and hydrogen in cycles of temporally separated pulses, without depositing a tungsten nucleation layer. Methods also include depositing tungsten directly on a substrate surface using alternating pulses of a chlorine-containing tungsten precursor and hydrogen without treating the substrate surface.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: May 22, 2018
    Assignee: Lam Research Corporation
    Inventors: Hanna Bamnolker, Joshua Collins, Tomas Sadilek, Hyeong Seop Shin, Xiaolan Ba, Raashina Humayun, Michal Danek, Lawrence Schloss
  • Patent number: 9972504
    Abstract: Methods of depositing tungsten into high aspect ratio features using a dep-etch-dep process integrating various deposition techniques with alternating pulses of surface modification and removal during etch are provided herein.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: May 15, 2018
    Assignee: Lam Research Corporation
    Inventors: Chiukin Steven Lai, Keren Jacobs Kanarik, Samantha Tan, Anand Chandrashekar, Teh-tien Su, Wenbing Yang, Michael Wood, Michal Danek
  • Patent number: 9953984
    Abstract: Disclosed herein are methods and related apparatus for formation of tungsten wordlines in memory devices. Also disclosed herein are methods and related apparatus for deposition of fluorine-free tungsten (FFW). According to various embodiments, the methods involve deposition of multi-component tungsten films using tungsten chloride (WClx) precursors and boron (B)-containing, silicon (Si)-containing or germanium (Ge)-containing reducing agents.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: April 24, 2018
    Assignee: Lam Research Corporation
    Inventors: Michal Danek, Hanna Bamnolker, Raashina Humayun, Juwen Gao
  • Publication number: 20180108529
    Abstract: Efficient integrated sequential deposition of alternating layers of dielectric and conductor, for example oxide/metal or metal nitride, e.g., SiO2/TiN, in a single tool, and even in a single process chamber enhances throughput without compromising quality when directly depositing a OMOM stack with many layers. Conductor and dielectric film deposition of a stack of at least 20 conductor/dielectric film pairs in the same processing tool or chamber, without breaking vacuum between the film depositions, such that there is no substantial cross-contamination between the conductor and dielectric film depositions, can be achieved.
    Type: Application
    Filed: May 11, 2017
    Publication date: April 19, 2018
    Inventors: William T. Lee, Bart J. van Schravendijk, David Charles Smith, Michal Danek, Patrick A. Van Cleemput, Ramesh Chandrasekharan
  • Publication number: 20180053660
    Abstract: Provided herein are methods and apparatuses for reducing line bending when depositing a metal such as tungsten, molybdenum, ruthenium, or cobalt into features on substrates by periodically exposing the feature to nitrogen, oxygen, or ammonia during atomic layer deposition, chemical vapor deposition, or sequential chemical vapor deposition to reduce interactions between metal deposited onto sidewalls of a feature. Methods are suitable for deposition into V-shaped features.
    Type: Application
    Filed: August 9, 2017
    Publication date: February 22, 2018
    Inventors: Adam Jandl, Sema Ermez, Lawrence Schloss, Sanjay Gopinath, Michal Danek, Siew Neo, Joshua Collins, Hanna Bamnolker
  • Publication number: 20170365513
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to ammonia vapor in a non-plasma process. Process parameters including exposure time, substrate temperature, and chamber pressure can be used to tune the inhibition profile. Also provided are methods of filling multiple adjacent lines with reduced or no line bending. The methods involve selectively inhibiting the tungsten nucleation to reduce sidewall growth during feature fill.
    Type: Application
    Filed: July 3, 2017
    Publication date: December 21, 2017
    Inventors: Tsung-Han Yang, Anand Chandrashekar, Jasmine Lin, Deqi Wang, Gang Liu, Michal Danek, Siew Neo