Patents by Inventor Michiaki Sugiyama

Michiaki Sugiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9818678
    Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.
    Type: Grant
    Filed: March 23, 2014
    Date of Patent: November 14, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
  • Patent number: 9640414
    Abstract: In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: March 19, 2016
    Date of Patent: May 2, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Michiaki Sugiyama, Nobuhiro Kinoshita
  • Patent number: 9455240
    Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: September 27, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
  • Publication number: 20160204082
    Abstract: In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.
    Type: Application
    Filed: March 19, 2016
    Publication date: July 14, 2016
    Inventors: Michiaki Sugiyama, Nobuhiro Kinoshita
  • Patent number: 9377825
    Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: June 28, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Minoru Shinohara, Makoto Araki, Michiaki Sugiyama
  • Patent number: 9355869
    Abstract: In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: August 17, 2013
    Date of Patent: May 31, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Michiaki Sugiyama, Nobuhiro Kinoshita
  • Publication number: 20150236003
    Abstract: A method of manufacturing a semiconductor device obtained by laminating a first semiconductor chip and a second semiconductor chip with different planar sizes when seen in a plan view on a wiring board via an adhesive material, in which the second semiconductor chip with a relatively larger planar size is mounted on the first semiconductor chip with a relatively smaller planar size. Also, after the first and second semiconductor chips are mounted, the first and second semiconductor chips are sealed with resin. Here, before sealing with the resin, a gap between the second semiconductor chip and the wiring board is previously sealed with the adhesive material used when the first and second semiconductor chips are mounted.
    Type: Application
    Filed: September 14, 2012
    Publication date: August 20, 2015
    Applicant: Renesas Electronics Corporation
    Inventors: Jumpei Konno, Takafumi Nishita, Kenji Sakata, Nobuhiro Kinoshita, Michiaki Sugiyama, Tsuyoshi Kida, Yoshihiro Ono
  • Publication number: 20140347809
    Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.
    Type: Application
    Filed: June 5, 2014
    Publication date: November 27, 2014
    Inventors: Minoru SHINOHARA, Makoto ARAKI, Michiaki SUGIYAMA
  • Publication number: 20140312498
    Abstract: To provide a semiconductor device having improved reliability. In a wiring board of BGA, an insulation layer has thereon a plurality of bonding leads. The insulation layer is comprised of a prepreg having a glass cloth and a resin layer not having the glass cloth. The prepreg has thereon the resin layer. The bonding leads are arranged directly on the soft resin layer and are therefore supported by this soft resin layer. When a load is applied to each of the bonding leads during flip chip bonding, the resin layer sinks, by which a stress applied to a semiconductor chip can be relaxed.
    Type: Application
    Filed: March 30, 2014
    Publication date: October 23, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Michiaki Sugiyama, Jumpei Konno
  • Publication number: 20140203431
    Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.
    Type: Application
    Filed: March 23, 2014
    Publication date: July 24, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Jumpei KONNO, Takafumi NISHITA, Nobuhiro KINOSHITA, Kazunori HASEGAWA, Michiaki SUGIYAMA
  • Publication number: 20140183759
    Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.
    Type: Application
    Filed: December 23, 2013
    Publication date: July 3, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
  • Patent number: 8754534
    Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: June 17, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Minoru Shinohara, Makoto Araki, Michiaki Sugiyama
  • Patent number: 8701972
    Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 22, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takafumi Nishita, Nobuhiro Kinoshita, Jumpei Konno, Michiaki Sugiyama, Kazunori Hasegawa
  • Publication number: 20140065767
    Abstract: In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.
    Type: Application
    Filed: August 17, 2013
    Publication date: March 6, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Michiaki Sugiyama, Nobuhiro Kinoshita
  • Publication number: 20140004661
    Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.
    Type: Application
    Filed: August 29, 2013
    Publication date: January 2, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Jumpei KONNO, Takafumi NISHITA, Nobuhiro KINOSHITA, Kazunori HASEGAWA, Michiaki SUGIYAMA
  • Patent number: 8534532
    Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.
    Type: Grant
    Filed: June 24, 2012
    Date of Patent: September 17, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
  • Publication number: 20130001274
    Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.
    Type: Application
    Filed: June 24, 2012
    Publication date: January 3, 2013
    Inventors: Jumpei KONNO, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
  • Patent number: 8319352
    Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.
    Type: Grant
    Filed: June 12, 2011
    Date of Patent: November 27, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Minoru Shinohara, Makoto Araki, Michiaki Sugiyama
  • Patent number: 8293575
    Abstract: The reliability of a semiconductor device is improved. A sealing resin (sealed body) is formed between a sub-substrate (first base member) and a base substrate (second base member) that are provided individually and distinctly to be integrated therewith, and then, the sub-substrate is electrically coupled to the second base member. As a means for electrically coupling the sub-substrate to the base substrate, lands (first lands) formed on the sub-substrate and lands (second lands) formed on the base substrate are disposed such that the respective positions thereof are aligned. After through holes are formed from the lands of the sub-substrate toward the lands of the base substrate, a solder member (conductive member) is formed in each of the through holes.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: October 23, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Hirai, Tomoaki Hashimoto, Takashi Kikuchi, Masatoshi Yasunaga, Michiaki Sugiyama
  • Patent number: 8222738
    Abstract: To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: July 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Ota, Michiaki Sugiyama, Toshikazu Ishikawa, Mikako Okada