Patents by Inventor Michiaki Sugiyama
Michiaki Sugiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20070125866Abstract: An IC card 1CD includes a frame member portion 1CB1, and an IC card main body 15 held in a state of being hung by a connecting portion 1CB2 in a frame thereof. The IC card main body 15 is made to constitute a card type information medium having a high functional performance having both of a function as a so-to-speak IC card and a function as a so-to-speak memory card having a capacity larger than that of the IC card and a function higher than that of the IC card capable of executing a security processing. An outer shape of the IC card main body 15 is formed in compliance with RS-MMC outer shape standard. A surface of a cap portion 1CB3 of the IC card main body 15 is printed with a desired character, pattern, diagram and photograph or the like by a printing method used in steps of fabricating a general IC card, and the IC card 15 is provided with higher acknowledgement performance, security performance and outlook.Type: ApplicationFiled: February 20, 2004Publication date: June 7, 2007Inventors: Hirotaka Nishizawa, Junichiro Osako, Kenji Osawa, Tamaki Wada, Michiaki Sugiyama
-
Patent number: 7227251Abstract: A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.Type: GrantFiled: April 26, 2005Date of Patent: June 5, 2007Assignee: Elpida Memory, Inc.Inventors: Kazuki Sakuma, Masayasu Kawamura, Yasushi Takahashi, Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano
-
Patent number: 7214622Abstract: In the assembly of a semiconductor device, improvement in the reliability of flip chip bonding is aimed at. By forming a dummy terminal in the end portion of the row of a plurality of terminals for a flip chip in the package substrate, the flow of flux or solder can be suppressed with the dummy terminal, and a solder layer can be formed on the plurality of terminals for a flip chip. Thereby, the thickness of the solder layer formed on each terminal for a flip chip can fully be secured, without making solder adhere to the wire connection terminal closely formed to the terminal for a flip chip. As a result, improvement in the reliability of flip chip bonding can be aimed at.Type: GrantFiled: July 25, 2005Date of Patent: May 8, 2007Assignee: Renesas Technology Corp.Inventors: Michiaki Sugiyama, Nobuhiro Kinoshita, Junpei Konno
-
Publication number: 20070013083Abstract: Improvement in the mountability of a semiconductor device is aimed at. By preparing a package substrate which has a plurality of lands of NSMD structure, and the taking-out wiring and dummy wiring which were connected to each of the lands, and have been arranged mutually in the location of 180° symmetry, and printing solder by a printing method to the lands after the package assembly, the variation in the height of the solder coat between lands can be reduced, and improvement in the mountability of LGA (semiconductor device) is aimed at.Type: ApplicationFiled: July 10, 2006Publication date: January 18, 2007Inventors: Takashi Kikuchi, Koichi Kanemoto, Michiaki Sugiyama, Hiroshi Kawakubo
-
Patent number: 7122883Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.Type: GrantFiled: December 3, 2004Date of Patent: October 17, 2006Assignees: Hitachi, Ltd., Hitachi Ulsi Systems Co., Ltd.Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura
-
Publication number: 20060205280Abstract: A semiconductor device comprising a first wiring board having a plurality of external connection terminals on one side, semiconductor chips mounted on the other side of the first wiring board and electrically connected to the first wiring board by a plurality of wires, a sealing resin for sealing the semiconductor chips and the wires, and a second wiring board having a plurality of contact points on one side and bonded to the top surface of the sealing resin on the other side, wherein the upper end portions of the loops of the plurality of wires for electrically connecting the first wiring board to the semiconductor chips are exposed from the top surface of the sealing resin and electrically connected to the second wiring board.Type: ApplicationFiled: March 10, 2006Publication date: September 14, 2006Inventors: Hirotaka Nishizawa, Tamaki Wada, Kenji Osawa, Junichiro Osako, Michiaki Sugiyama
-
Publication number: 20060151614Abstract: A multifunction card device has an external connection terminal, an interface controller, a memory, and the security controller connected to the interface controller and the external connection terminal. The interface controller has a plurality of interface control modes, and controls an external-interface action and a memory interface action by the control mode according to the instruction from the outside. The external connection terminals have an individual terminal individualized for every interface control mode, and a communalized common terminal. A clock input terminal, a power supply terminal, and an earthing terminal are included in the common terminals. A data terminal, and a dedicated terminal of the security controller are included in the individual terminals. Partial communalization and individualization of an external connection terminal attain a guarantee of the reliability of an interface, and increase control of physical magnitude to some kinds of interface control modes.Type: ApplicationFiled: July 3, 2003Publication date: July 13, 2006Inventors: Hirotaka Nishizawa, Akira Higuchi, Kenji Osawa, Junichiro Osako, Tamaki Wada, Michiaki Sugiyama
-
Publication number: 20060087016Abstract: An IC card according to the present invention reduces or prevents a deterioration or damage on an electronic device to which the IC card is mounted. A buffer section made of a thermoplastic resin formed by a plastic injection molding is provided at the outer peripheral face of a memory card whose appearance is partly composed of a sealing section made of a thermosetting resin formed by a transfer molding without providing a cap. The buffer section has a taper formed at the outer peripheral corner, and further, the buffer section is softer than the sealing section and has a smooth surface. When the memory card is mounted to an electronic device, the buffer section is brought into contact with connector pins or a guide rail of a connector of the electronic device, thereby being capable of reducing or preventing the deterioration or damage on the connector.Type: ApplicationFiled: October 18, 2005Publication date: April 27, 2006Inventors: Tamaki Wada, Hirotaka Nishizawa, Michiaki Sugiyama, Junichiro Osako
-
Patent number: 7012321Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.Type: GrantFiled: March 4, 2003Date of Patent: March 14, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura
-
Publication number: 20060030075Abstract: In the assembly of a semiconductor device, improvement in the reliability of flip chip bonding is aimed at. By forming a dummy terminal in the end portion of the row of a plurality of terminals for a flip chip in the package substrate, the flow of flux or solder can be suppressed with the dummy terminal, and a solder layer can be formed on the plurality of terminals for a flip chip. Thereby, the thickness of the solder layer formed on each terminal for a flip chip can fully be secured, without making solder adhere to the wire connection terminal closely formed to the terminal for a flip chip. As a result, improvement in the reliability of flip chip bonding can be aimed at.Type: ApplicationFiled: July 25, 2005Publication date: February 9, 2006Inventors: Michiaki Sugiyama, Nobuhiro Kinoshita, Junpei Konno
-
Publication number: 20050253239Abstract: This invention is to provide an ultra-miniaturized, thin-sized memory card provided with a mechanism for preventing a wrong insertion to a memory card slot. A multi-function memory card is composed of a card body and a cap for housing the card body. The card body is made of mold resin that encapsulates plural semiconductor chips mounted on a main surface of a wiring substrate. The card body is housed into the cap with the back face of the wiring substrate facing outward. Guide channels are provided at both side faces of the cap for preventing that the card is inserted upside down. Further, a convex section is provided at the trailing edge of the cap for preventing that the card is inserted in the wrong direction.Type: ApplicationFiled: April 25, 2005Publication date: November 17, 2005Inventors: Hirotaka Nishizawa, Kenji Osawa, Junichiro Osako, Tamaki Wada, Michiaki Sugiyama, Takashi Totsuka
-
Publication number: 20050252978Abstract: To realize compatibility with an SIM card and adaptation to a high-speed memory access in an IC card module having a microcomputer and a memory card controller. An IC card module includes a plurality of first external connecting terminals and a plurality of second external connecting terminals both exposed to one surface of a card substrate, a microcomputer connected to the first external connecting terminals, a memory controller connected to the second external connecting terminals, and a volatile memory connected to the memory controller. The shape of the card substrate and the layout of the first external connecting terminals are based on a standard of plug-in UICC of ETSI TS 102 221 V4.4.0 (2001-10) or have compatibility. The second external connecting terminals are disposed outside the minimum range of the terminal layout based on the standard for the first external connecting terminals.Type: ApplicationFiled: May 10, 2005Publication date: November 17, 2005Inventors: Hirotaka Nishizawa, Takashi Totsuka, Kenji Osawa, Junichiro Osako, Tamaki Wada, Michiaki Sugiyama
-
Publication number: 20050184380Abstract: A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.Type: ApplicationFiled: April 26, 2005Publication date: August 25, 2005Inventors: Kazuki Sakuma, Masayasu Kawamura, Yasushi Takahashi, Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano
-
Publication number: 20050094433Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.Type: ApplicationFiled: December 3, 2004Publication date: May 5, 2005Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura
-
Publication number: 20050094463Abstract: An antenna connection function for a noncontact interface is provided by suppressing a modification in a pin arrangement and a pin shape of a memory card that does not correspond to the noncontact interface. Two antenna connecting pins having the memory card are divided into two areas in which a size of one potential supply pin is the largest and used as a split pin arranged at intervals. Because a size of the two antenna connecting pins is at maximum as large as the size of the potential supply pin, the two antenna connecting pins are provided and the memory card that corresponds to the noncontact interface is obtained by devoting a pin area having the size of the one potential supply pin to the memory card that does not correspond to the noncontact interface. Accordingly, the pin area of the memory card that corresponds to the noncontact interface can be formed without departing from the pin area of the memory card that does not correspond to the noncontact interface.Type: ApplicationFiled: October 12, 2004Publication date: May 5, 2005Inventors: Hirotaka Nishizawa, Akira Higuchi, Kenji Osawa, Junichiro Osako, Tamaki Wada, Michiaki Sugiyama
-
Patent number: 6885092Abstract: A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.Type: GrantFiled: December 2, 1999Date of Patent: April 26, 2005Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Kazuki Sakuma, Masayasu Kawamura, Yasushi Takahashi, Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano
-
Publication number: 20050052924Abstract: The present invention provides a memory card equipped with an interface controller connected to external connecting terminals, a memory connected to the interface controller, and a security controller connected to the interface controller. A second external connecting terminal capable of supplying an operating power supply to the security controller is provided aside from a first external connecting terminal which supplies an operating power supply to the interface controller and the memory. An interface unit of the interface controller connected to the security controller receives the operating power supply from the second external connecting terminal and thereby enables a stop of the supply of the operating power supply from the first external connecting terminal. Even if the supply of the operating power supply to the interface controller is cut off, the output of the interface unit is not brought to an indefinite state.Type: ApplicationFiled: August 6, 2004Publication date: March 10, 2005Inventors: Hirotaka Nishizawa, Akira Higuchi, Kenji Osawa, Tamaki Wada, Michiaki Sugiyama, Junichiro Osako
-
Patent number: 6853089Abstract: In the manufacture of a semiconductor device by adopting a block molding method wherein a semiconductor chip is fixed onto a wiring substrate through an adhesive, the occurrence of a defect caused by flowing-out of the adhesive is to be prevented. The semiconductor device according to the present invention comprises a wiring substrate, the wiring substrate having a main surface, an insulating film formed on the main surface, and electrodes formed on the main surface so as to be exposed from the insulating film, a semiconductor chip fixed through an adhesive onto the insulating film formed on the main surface of the wiring substrate, conductive wires for connecting the electrodes on the main surface of the wiring substrate and electrodes on the semiconductor chip with each other, and a seal member, i.e.Type: GrantFiled: August 22, 2002Date of Patent: February 8, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Mikako Ujiie, Michiaki Sugiyama, Kazunari Suzuki, Masachika Masuda, Tamaki Wada
-
Publication number: 20040197959Abstract: A method of manufacturing a semiconductor device, comprises providing a wiring substrate having a main surface, an insulating film formed on the main surface, and electrodes formed on the main surface so as to be exposed from the insulating film. A semiconductor chip is adhesively fixed to the insulating film. Conductive wires connect the electrodes on the main surface of the wiring substrate and electrodes on the chip. A groove is formed between the chip and the electrodes on the substrate. A protruding portion of the adhesive stays within the groove and does not reach the electrodes on the substrate.Type: ApplicationFiled: April 16, 2004Publication date: October 7, 2004Applicants: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Mikako Ujiie, Michiaki Sugiyama, Kazunari Suzuki, Masachika Masuda, Tamaki Wada
-
Patent number: 6750080Abstract: Two semiconductor chips are bonded to each other with the rear surfaces of the respective semiconductor chips faced to each other, so that two longer sides of the semiconductor chips may confront the side of leads, and supporting leads are bonded and fixed onto the circuit forming surface of one of the semiconductor chips. The semiconductor chips are further bonded to each other in a state where the positions of the respective semiconductor chips are staggered relative to each other so that electrodes of one semiconductor chip may lie outside the other longer side of the other semiconductor chip, and that electrodes of the second semiconductor chip may lie outside the other longer side of the first semiconductor chip.Type: GrantFiled: February 25, 2003Date of Patent: June 15, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Tomoko Higashino, Takafumi Nishita, Hiroshi Ohno