Patents by Inventor Michiaki Sugiyama

Michiaki Sugiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030164542
    Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.
    Type: Application
    Filed: March 4, 2003
    Publication date: September 4, 2003
    Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura
  • Publication number: 20030153134
    Abstract: A method for manufacturing a semiconductor device including providing first and second semiconductor chips each having a main surface having a semiconductor element and a plurality of external terminals, and a lower surface respectively opposing the main surface. A first lead frame is provided which has a frame body which supports outer portions and inner portions extending from the outer portions, and a second lead frame is provided which has a frame body which supports outer portions and inner portions extending from the outer portions. After electrically connecting the external terminals to the inner portions of the lead frames and resin-sealing the first and second semiconductor chips so that the first and second lead frames are superimposed, the frame body of the second lead frame is removed and a first processing fluid is applied to the outer portions of the first lead frame and the second lead frame.
    Type: Application
    Filed: February 27, 2003
    Publication date: August 14, 2003
    Inventors: Youichi Kawata, Kouji Koizumi, Michiaki Sugiyama, Atsushi Fujishima, Yasuyuki Nakajima, Takatoshi Hagiwara
  • Publication number: 20030122262
    Abstract: Semiconductor chips (4), (5) are bonded and fixed to each other in a state where the rear surfaces of the respective semiconductor chips are faced to each other so that the other longer latus (4A2) of the semiconductor chip (4) and one longer latus (5A1) of the semiconductor chip (5) may confront the side of leads (10B), and supporting leads (8) are bonded and fixed onto the circuit forming surface (4A) of the semiconductor chip (4) or the circuit forming surface (5A) of the semiconductor chip (5). Owing to such a construction, the structure of a semiconductor device can be thinned.
    Type: Application
    Filed: February 25, 2003
    Publication date: July 3, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Tomoko Higashino, Takafumi Nishita, Hiroshi Ohno
  • Patent number: 6555918
    Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: April 29, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura
  • Patent number: 6551858
    Abstract: A semiconductor device according to this invention, wherein two semiconductor chips are sealed by one resin body using two lead frames, includes a wide part extending in the width direction of dam bars, the width of one dam bar being narrower than the width of another dam bar, and the two lead frames are joined by welding outside the resin body after sealing them with resin.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: April 22, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Youichi Kawata, Kouji Koizumi, Michiaki Sugiyama, Atsushi Fujishima, Yasuyuki Nakajima, Takatoshi Hagiwara
  • Patent number: 6552437
    Abstract: Semiconductor chips (4), (5) are bonded and fixed to each other in a state where the rear surfaces of the respective semiconductor chips are faced to each other so that the other longer latus (4A2) of the semiconductor chip (4) and one longer latus (5A1) of the semiconductor chip (5) may confront the side of leads (10B), and supporting leads (8) are bonded and fixed onto the circuit forming surface (4A) of the semiconductor chip (4) or the circuit forming surface (5A) of the semiconductor chip (5). Owing to such a construction, the structure of a semiconductor device can be thinned.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: April 22, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Tomoko Higashino, Takafumi Nishita, Hiroshi Ohno
  • Publication number: 20030052419
    Abstract: In the manufacture of a semiconductor device by adopting a block molding method wherein a semiconductor chip is fixed onto a wiring substrate through an adhesive, the occurrence of a defect caused by flowing-out of the adhesive is to be prevented. The semiconductor device according to the present invention comprises a wiring substrate, the wiring substrate having a main surface, an insulating film formed on the main surface, and electrodes formed on the main surface so as to be exposed from the insulating film, a semiconductor chip fixed through an adhesive onto the insulating film formed on the main surface of the wiring substrate, conductive wires for connecting the electrodes on the main surface of the wiring substrate and electrodes on the semiconductor chip with each other, and a seal member, i.e.
    Type: Application
    Filed: August 22, 2002
    Publication date: March 20, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Mikako Ujiie, Michiaki Sugiyama, Kazunari Suzuki, Masachika Masuda, Tamaki Wada
  • Patent number: 6501183
    Abstract: A first semiconductor chip (2) is bonded and secured to a second semiconductor chip (3) with a back surface of the first semiconductor chip (2) and a circuit forming surface (3X) of the second semiconductor chip (3) facing each other, and an inner portion of a support lead (6) is bonded and secured to the circuit forming surface (3X) of the second semiconductor chip (3). Such a configuration makes it possible to provide a semiconductor with a reduced thickness.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: December 31, 2002
    Assignees: Hitachi, Ltd., Hitachi USLI Systems Co., Ltd.
    Inventors: Kouichi Kanemoto, Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Mikako Kimura
  • Patent number: 6479322
    Abstract: A semiconductor device according to this invention, wherein two semiconductor chips are sealed by one resin body using two lead frames, includes a wide part extending in the width direction of dam bars, the width of one dam bar being narrower than the width of another dam bar, and the two lead frames are joined by welding outside the resin body after sealing them with resin.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: November 12, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Youichi Kawata, Kouji Koizumi, Michiaki Sugiyama, Atsushi Fujishima, Yasuyuki Nakajima, Takatoshi Hagiwara
  • Publication number: 20020119598
    Abstract: A semiconductor device according to this invention, wherein two semiconductor chips are sealed by one resin body using two lead frames, comprises a wide part extending in the width direction of dam bars, the width of one dam bar being narrower than the width of another dam bar, and the two lead frames are joined by soldering outside the resin body after sealing them with resin.
    Type: Application
    Filed: April 29, 2002
    Publication date: August 29, 2002
    Inventors: Youichi Kawata, Kouji Koizumi, Michiaki Sugiyama, Atsushi Fujishima, Yasuyuki Nakajima, Takatoshi Hagiwara
  • Publication number: 20020102763
    Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.
    Type: Application
    Filed: March 25, 2002
    Publication date: August 1, 2002
    Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura
  • Patent number: 6410365
    Abstract: A semiconductor device according to this invention, wherein two semiconductor chips are sealed by one resin body using two lead frames, includes a wide part extending in the width direction of dam bars, the width of one dam bar being narrower than the width of another dam bar, and the two lead frames are joined by welding outside the resin body after sealing them with resin.
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: June 25, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Youichi Kawata, Kouji Koizumi, Michiaki Sugiyama, Atsushi Fujishima, Yasuyuki Nakajima, Takatoshi Hagiwara
  • Patent number: 6410987
    Abstract: A first semiconductor chip (2) is bonded and secured to a second semiconductor chip (3) with a back surface of the first semiconductor chip (2) and a circuit forming surface (3X) of the second semiconductor chip (3) facing each other, and an inner portion of a support lead (6) is bonded and secured to the circuit forming surface (3X) of the second semiconductor chip (3). Such a configuration makes it possible to provide a semiconductor with a reduced thickness.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: June 25, 2002
    Assignees: Hitachi, Ltd., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Kouichi Kanemoto, Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Mikako Kimura
  • Publication number: 20020064903
    Abstract: A semiconductor device according to this invention, wherein two semiconductor chips are sealed by one resin body using two lead frames, comprises a wide part extending in the width direction of dam bars, the width of one dam bar being narrower than the width of another dam bar, and the two lead frames are joined by soldering outside the resin body after sealing them with resin.
    Type: Application
    Filed: January 2, 2002
    Publication date: May 30, 2002
    Inventors: Youichi Kawata, Kouji Koizumi, Michiaki Sugiyama, Atsushi Fujishima, Yasuyuki Nakajima, Takatoshi Hagiwara
  • Patent number: 6383845
    Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: May 7, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura
  • Publication number: 20020014686
    Abstract: A first semiconductor chip (2) is bonded and secured to a second semiconductor chip (3) with a back surface of the first semiconductor chip (2) and a circuit forming surface (3X) of the second semiconductor chip (3) facing each other, and an inner portion of a support lead (6) is bonded and secured to the circuit forming surface (3X) of the second semiconductor chip (3). Such a configuration makes it possible to provide a semiconductor with a reduced thickness.
    Type: Application
    Filed: July 27, 2001
    Publication date: February 7, 2002
    Applicant: Hitachi, Ltd. and Hitachi ULSI Systems Co., Ltd.
    Inventors: Kouichi Kanemoto, Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Mikako Kimura
  • Patent number: 6297545
    Abstract: In a package of an LOC (Lead On Chip) structure in which inner lead portions are partially arranged over a major face of a semiconductor chip, there is disclosed a technique for thinning the package and speeding up signal transmission. Specifically, by partially reducing the thicknesses of the signal inner leads arranged over the major face of the semiconductor chip, the thickness of a sealing resin is reduced while ensuring the mechanical strength of the package. Moreover, the signal inner leads arranged over the major face of the semiconductor chip are arranged at predetermined spacings from the major face of the semiconductor chip. The power supplying inner leads are bonded to the major face of the semiconductor chip, thus providing a package having a reduced parasitic capacitance.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: October 2, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Michiaki Sugiyama, Tamaki Wada, Masachika Masuda
  • Publication number: 20010023088
    Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.
    Type: Application
    Filed: May 15, 2001
    Publication date: September 20, 2001
    Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura
  • Patent number: 6285074
    Abstract: In a package of an LOC (Lead On Chip) structure in which inner lead portions are partially arranged over a major face of a semiconductor chip, there is disclosed a technique for thinning the package and speeding up signal transmission. Specifically, by partially reducing the thicknesses of the signal inner leads arranged over the major face of the semiconductor chip, the thickness of a sealing resin is reduced while ensuring the mechanical strength of the package. Moreover, the signal inner leads arranged over the major face of the semiconductor chip are arranged at predetermined spacings from the major face of the semiconductor chip. The power supplying inner leads are bonded to the major face of the semiconductor chip, thus providing a package having a reduced parasitic capacitance.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: September 4, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Michiaki Sugiyama, Tamaki Wada, Masachika Masuda
  • Patent number: 6252299
    Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: June 26, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Systemc Co., Ltd.
    Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura