Patents by Inventor Michiaki Sugiyama
Michiaki Sugiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8293575Abstract: The reliability of a semiconductor device is improved. A sealing resin (sealed body) is formed between a sub-substrate (first base member) and a base substrate (second base member) that are provided individually and distinctly to be integrated therewith, and then, the sub-substrate is electrically coupled to the second base member. As a means for electrically coupling the sub-substrate to the base substrate, lands (first lands) formed on the sub-substrate and lands (second lands) formed on the base substrate are disposed such that the respective positions thereof are aligned. After through holes are formed from the lands of the sub-substrate toward the lands of the base substrate, a solder member (conductive member) is formed in each of the through holes.Type: GrantFiled: July 13, 2010Date of Patent: October 23, 2012Assignee: Renesas Electronics CorporationInventors: Tatsuya Hirai, Tomoaki Hashimoto, Takashi Kikuchi, Masatoshi Yasunaga, Michiaki Sugiyama
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Patent number: 8222738Abstract: To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device.Type: GrantFiled: August 18, 2011Date of Patent: July 17, 2012Assignee: Renesas Electronics CorporationInventors: Yusuke Ota, Michiaki Sugiyama, Toshikazu Ishikawa, Mikako Okada
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Patent number: 8138022Abstract: A first conductive member made of metal is provided over a first wiring substrate, which is a mounting substrate in the lower tier, a through hole is provided in a second wiring substrate, which is a mounting substrate in the upper tier, at a position corresponding to the first conductive member in a plan view, and a wiring is exposed at the sidewall of the through hole. The first conductive member is inserted into the through hole on the corresponding first wiring substrate side and the first wiring substrate and the second wiring substrate are electrically coupled by filling the through hole with a second conductive member. an electrode pad that is electrically coupled to the second conductive member and over which a semiconductor member in the upper tier is mounted is formed on the main surface side of the second wiring substrate.Type: GrantFiled: June 4, 2010Date of Patent: March 20, 2012Assignee: Renesas Electronics CorporationInventors: Michiaki Sugiyama, Takashi Miwa, Toshikazu Ishikawa, Tatsuya Hirai
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Patent number: 8084869Abstract: A technique permitting the reduction in size of a semiconductor device is provided. In a BGA type semiconductor device with a semiconductor chip flip-chip-bonded onto a wiring substrate, bump electrodes of the semiconductor chip are coupled to lands formed at an upper surface of the wiring substrate. The lands at the upper surface of the wiring substrate are coupled electrically to solder balls formed on a lower surface of the wiring substrate. Therefore, the lands include first type lands with lead-out lines coupled thereto and second type lands with lead-out lines not coupled thereto but with vias formed just thereunder. The lands are arrayed in six or more rows at equal pitches in an advancing direction of the rows. However, a row-to-row pitch is not made an equal pitch. In land rows which are likely to cause a short-circuit, the pitch between adjacent rows is made large, while in land rows which are difficult to cause a short-circuit, the pitch between adjacent rows is made small.Type: GrantFiled: June 5, 2009Date of Patent: December 27, 2011Assignee: Renesas Electronics CorporationInventors: Takashi Miwa, Michiaki Sugiyama, Kazumasa Yanagisawa
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Publication number: 20110300672Abstract: To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device.Type: ApplicationFiled: August 18, 2011Publication date: December 8, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yusuke OTA, Michiaki SUGIYAMA, Toshikazu ISHIKAWA, Mikako OKADA
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Publication number: 20110233788Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.Type: ApplicationFiled: June 12, 2011Publication date: September 29, 2011Inventors: MINORU SHINOHARA, Makoto Araki, Michiaki Sugiyama
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Publication number: 20110227234Abstract: A multifunction card device has an external connection terminal, an interface controller, a memory, and the security controller connected to the interface controller and the external connection terminal. The interface controller has a plurality of interface control modes, and controls an external-interface action and a memory interface action by the control mode according to the instruction from the outside. The external connection terminals have an individual terminal individualized for every interface control mode, and a communalized common terminal. A clock input terminal, a power supply terminal, and an earthing terminal are included in the common terminals. A data terminal, and a dedicated terminal of the security controller are included in the individual terminals. Partial communalization and individualization of an external connection terminal attain a guarantee of the reliability of an interface, and increase control of physical magnitude to some kinds of interface control modes.Type: ApplicationFiled: June 3, 2011Publication date: September 22, 2011Inventors: Hirotaka Nishizawa, Akira Higuchi, Kenji Osawa, Junichiro Osako, Tamaki Wada, Michiaki Sugiyama
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Patent number: 8021932Abstract: To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device.Type: GrantFiled: April 27, 2009Date of Patent: September 20, 2011Assignee: Renesas Electronics CorporationInventors: Yusuke Ota, Michiaki Sugiyama, Toshikazu Ishikawa, Mikako Okada
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Patent number: 7989960Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.Type: GrantFiled: February 4, 2009Date of Patent: August 2, 2011Assignee: Renesas Electronics CorporationInventors: Minoru Shinohara, Makoto Araki, Michiaki Sugiyama
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Patent number: 7971791Abstract: A multifunction card device has an external connection terminal, an interface controller, a memory, and the security controller connected to the interface controller and the external connection terminal. The interface controller has a plurality of interface control modes, and controls an external-interface action and a memory interface action by the control mode according to the instruction from the outside. The external connection terminals have an individual terminal individualized for every interface control mode, and a communalized common terminal. A clock input terminal, a power supply terminal, and an earthing terminal are included in the common terminals. A data terminal, and a dedicated terminal of the security controller are included in the individual terminals. Partial communalization and individualization of an external connection terminal attain a guarantee of the reliability of an interface, and increase control of physical magnitude to some kinds of interface control modes.Type: GrantFiled: July 3, 2003Date of Patent: July 5, 2011Assignee: Renesas Electronics CorporationInventors: Hirotaka Nishizawa, Akira Higuchi, Kenji Osawa, Junichiro Osako, Tamaki Wada, Michiaki Sugiyama
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Patent number: 7971793Abstract: The present invention provides a memory card equipped with an interface controller connected to external connecting terminals, a memory connected to the interface controller, and a security controller connected to the interface controller. A second external connecting terminal capable of supplying an operating power supply to the security controller is provided aside from a first external connecting terminal which supplies an operating power supply to the interface controller and the memory. An interface unit of the interface controller connected to the security controller receives the operating power supply from the second external connecting terminal and thereby enables a stop of the supply of the operating power supply from the first external connecting terminal. Even if the supply of the operating power supply to the interface controller is cut off, the output of the interface unit is not brought to an indefinite state.Type: GrantFiled: November 27, 2007Date of Patent: July 5, 2011Assignee: Renesas Electronics CorporationInventors: Hirotaka Nishizawa, Akira Higuchi, Kenji Osawa, Tamaki Wada, Michiaki Sugiyama, Junichiro Osako
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Patent number: 7946500Abstract: An antenna connection function for a noncontact interface is provided by suppressing a modification in a pin arrangement and a pin shape of a memory card that does not correspond to the noncontact interface. Two antenna connecting pins having the memory card are divided into two areas in which a size of one potential supply pin is the largest and used as a split pin arranged at intervals. Because a size of the two antenna connecting pins is at maximum as large as the size of the potential supply pin, the two antenna connecting pins are provided and the memory card that corresponds to the noncontact interface is obtained by devoting a pin area having the size of the one potential supply pin to the memory card that does not correspond to the noncontact interface. Accordingly, the pin area of the memory card that corresponds to the noncontact interface can be formed without departing from the pin area of the memory card that does not correspond to the noncontact interface.Type: GrantFiled: December 16, 2007Date of Patent: May 24, 2011Assignee: Renesas Electronics CorporationInventors: Hirotaka Nishizawa, Akira Higuchi, Kenji Osawa, Junichiro Osako, Tamaki Wada, Michiaki Sugiyama
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Publication number: 20110076800Abstract: The reliability of a semiconductor device is improved. A sealing resin (sealed body) is formed between a sub-substrate (first base member) and a base substrate (second base member) that are provided individually and distinctly to be integrated therewith, and then, the sub-substrate is electrically coupled to the second base member. As a means for electrically coupling the sub-substrate to the base substrate, lands (first lands) formed on the sub-substrate and lands (second lands) formed on the base substrate are disposed such that the respective positions thereof are aligned. After through holes are formed from the lands of the sub-substrate toward the lands of the base substrate, a solder member (conductive member) is formed in each of the through holes.Type: ApplicationFiled: July 13, 2010Publication date: March 31, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tatsuya HIRAI, Tomoaki HASHIMOTO, Takashi KIKUCHI, Masatoshi YASUNAGA, Michiaki SUGIYAMA
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Publication number: 20100330742Abstract: A first conductive member made of metal is provided over a first wiring substrate, which is a mounting substrate in the lower tier, a through hole is provided in a second wiring substrate, which is a mounting substrate in the upper tier, at a position corresponding to the first conductive member in a plan view, and a wiring is exposed at the sidewall of the through hole. The first conductive member is inserted into the through hole on the corresponding first wiring substrate side and the first wiring substrate and the second wiring substrate are electrically coupled by filling the through hole with a second conductive member. an electrode pad that is electrically coupled to the second conductive member and over which a semiconductor member in the upper tier is mounted is formed on the main surface side of the second wiring substrate.Type: ApplicationFiled: June 4, 2010Publication date: December 30, 2010Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Michiaki Sugiyama, Takashi Miwa, Toshikazu Ishikawa, Tatsuya Hirai
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Publication number: 20100314757Abstract: In a POP semiconductor device, a technology is provided which can increase the degree of freedom of semiconductor packages to be combined. A first metal conductive member is placed on a first wiring substrate which is a lower mounting substrate and a second metal conductive member is placed on a second wiring substrate which is an upper mounting substrate. By joining the corresponding portions of the first and second conductive members, the first and second wiring substrates are electrically coupled to each other. An electrode pad which is electrically coupled to the second conductive member and will have an upper semiconductor member 32 mounted thereon is formed on the main surface side of the second wiring substrate, and the electrode pad is also placed at a position planarly overlapping the lower semiconductor chip.Type: ApplicationFiled: May 11, 2010Publication date: December 16, 2010Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Michiaki SUGIYAMA, Takashi MIWA, Toshikazu ISHIKAWA
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Patent number: 7804176Abstract: This invention is to provide a nonvolatile memory device that enhances a size reduction and mass productivity while ensuring reliability and signal transmission performance. A nonvolatile memory chip having a first side formed with no pads and a second side formed with pads is mounted on a mounting substrate. A control chip for controlling the nonvolatile memory chip is mounted on the nonvolatile memory chip. The control chip has a first pad row corresponding to the pads of the nonvolatile memory chip. The first pad row is mounted adjacent to the first side of the nonvolatile memory chip. The first pad row of the control chip and a first electrode row formed on the mounting substrate are connected via a first wire group. The pads of the nonvolatile memory chip and a second electrode row formed on the mounting substrate are connected via a second wire group. The first electrode row and the second electrode row are connected through wirings formed in the mounting substrate.Type: GrantFiled: January 23, 2007Date of Patent: September 28, 2010Assignee: Renesas Electronics CorporationInventors: Kazuko Hanawa, Takashi Kikuchi, Koichi Kanemoto, Michiaki Sugiyama, Chikako Imura
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Patent number: 7669773Abstract: To realize compatibility with an SIM card and adaptation to a high-speed memory access in an IC card module having a microcomputer and a memory card controller. An IC card module includes a plurality of first external connecting terminals and a plurality of second external connecting terminals both exposed to one surface of a card substrate, a microcomputer connected to the first external connecting terminals, a memory controller connected to the second external connecting terminals, and a volatile memory connected to the memory controller. The shape of the card substrate and the layout of the first external connecting terminals are based on a standard of plug-in UICC of ETSI TS 102 221 V4.4.0 (2001-10) or have compatibility. The second external connecting terminals are disposed outside the minimum range of the terminal layout based on the standard for the first external connecting terminals.Type: GrantFiled: October 18, 2007Date of Patent: March 2, 2010Assignee: Renesas Technology Corp.Inventors: Hirotaka Nishizawa, Takashi Totsuka, Kenji Osawa, Junichiro Osako, Tamaki Wada, Michiaki Sugiyama
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Publication number: 20100019382Abstract: A technique permitting the reduction in size of a semiconductor device is provided. In a BGA type semiconductor device with a semiconductor chip flip-chip-bonded onto a wiring substrate, bump electrodes of the semiconductor chip are coupled to lands formed at an upper surface of the wiring substrate. The lands at the upper surface of the wiring substrate are coupled electrically to solder balls formed on a lower surface of the wiring substrate. Therefore, the lands include first type lands with lead-out lines coupled thereto and second type lands with lead-out lines not coupled thereto but with vias formed just thereunder. The lands are arrayed in six or more rows at equal pitches in an advancing direction of the rows. However, a row-to-row pitch is not made an equal pitch. In land rows which are likely to cause a short-circuit, the pitch between adjacent rows is made large, while in land rows which are difficult to cause a short-circuit, the pitch between adjacent rows is made small.Type: ApplicationFiled: June 5, 2009Publication date: January 28, 2010Inventors: Takashi MIWA, Michiaki Sugiyama, Kazumasa Yanagisawa
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Publication number: 20090294978Abstract: To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device.Type: ApplicationFiled: April 27, 2009Publication date: December 3, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yusuke OTA, Michiaki SUGIYAMA, Toshikazu ISHIKAWA, Mikako OKADA
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Publication number: 20090200680Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.Type: ApplicationFiled: February 4, 2009Publication date: August 13, 2009Inventors: Minoru SHINOHARA, Makoto Araki, Michiaki Sugiyama