Abstract: In a package of an LOC (Lead On Chip) structure in which inner lead portions are partially arranged over a major face of a semiconductor chip, there is disclosed a technique for thinning the package and speeding up signal transmission.

Abstract: In a package having an LOC (Lead On Chip) structure in which inner lead portions are partially arranged over a major face of a semiconductor chip, there is a technique for thinning the package and speeding up signal transmission. Specifically, by partially reducing the thicknesses of the signal inner leads arranged over the major face of the semiconductor chip, the thickness of a sealing resin is reduced while ensuring the mechanical strength of the package. Moreover, the signal inner leads arranged over the major face of the semiconductor chip are arranged at predetermined spacings from the major face of the semiconductor chip. The power supplying inner leads are bonded to the major face of the semiconductor chip, thus providing a package having a reduced parasitic capacitance.

Abstract: Disclosed is a packaged semiconductor device, e.g., of the lead-on-chip type, having reduced thickness, by providing only an adhesive (without a base film) between inner lead portions of the leads and the semiconductor chip to adhere the inner-lead portions to the chip. The adhesive can cover a dicing area of the semiconductor chip, and, in general, can cover edge parts of the chip (and extend beyond the edge of the chip) to prevent short-circuits between the inner lead portions and the semiconductor chip. The outer lead portions have a lower outer end part and a part, closer to the package body, which extends upward obliquely; has stopper members on the obliquely extending part; and has an obliquely extending part with a greater width than a width of the outer end parts of the outer lead portions, to facilitate stacking of packaged semiconductor chips on each other, e.g., for mounting on a printed circuit board. Packaged semiconductor chips having, e.g.