Patents by Inventor Mie Matsuo

Mie Matsuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942176
    Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: March 26, 2024
    Assignee: Kioxia Corporation
    Inventors: Tomoya Sanuki, Xu Li, Masayuki Miura, Takayuki Miyazaki, Toshio Fujisawa, Hiroto Nakai, Hideko Mukaida, Mie Matsuo
  • Publication number: 20240099013
    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Applicant: Kioxia Corporation
    Inventors: Yoshiaki FUKUZUMI, Hideaki AOCHI, Mie MATSUO, Kenichiro YOSHII, Koichiro SHINDO, Kazushige KAWASAKI, Tomoya SANUKI
  • Patent number: 11871576
    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: January 9, 2024
    Assignee: Kioxia Corporation
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi, Mie Matsuo, Kenichiro Yoshii, Koichiro Shindo, Kazushige Kawasaki, Tomoya Sanuki
  • Patent number: 11862510
    Abstract: A semiconductor device manufacturing method of an embodiment includes forming a first layer in a region of a first substrate excluding an outer peripheral portion thereof; forming a first semiconductor circuit above the first layer; for a second semiconductor circuit on a second substrate; forming a second layer with a predetermined width at an outer peripheral portion of the second substrate; bonding a surface of the first substrate on a side provided with the first semiconductor circuit and a surface of the second substrate on a side provided with the second semiconductor circuit; and applying tensile stress to the first layer and the second layer to debond the first layer and the second layer, thereby forming the second substrate including the first semiconductor circuit and the second semiconductor circuit.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: January 2, 2024
    Assignee: Kioxia Corporation
    Inventor: Mie Matsuo
  • Publication number: 20230245927
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first semiconductor layer including impurity atoms with a first density, on a first substrate, forming a second semiconductor layer including impurity atoms with a second density higher than the first density, on the first semiconductor layer, and forming a porous layer resulting from porosification of at least a portion of the second semiconductor layer. The method further includes forming a first film including a device, on the porous layer, providing a second substrate provided with a second film including a device, and bonding the first and second substrates to sandwich the first and second films. The method further includes separating the first and second substrates from each other such that a first portion of the porous layer remains on the first substrate and a second portion of the porous layer remains on the second substrate.
    Type: Application
    Filed: April 6, 2023
    Publication date: August 3, 2023
    Applicant: Kioxia Corporation
    Inventors: Hidekazu HAYASHI, Mie MATSUO
  • Patent number: 11652000
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first semiconductor layer including impurity atoms with a first density, on a first substrate, forming a second semiconductor layer including impurity atoms with a second density higher than the first density, on the first semiconductor layer, and forming a porous layer resulting from porosification of at least a portion of the second semiconductor layer. The method further includes forming a first film including a device, on the porous layer, providing a second substrate provided with a second film including a device, and bonding the first and second substrates to sandwich the first and second films. The method further includes separating the first and second substrates from each other such that a first portion of the porous layer remains on the first substrate and a second portion of the porous layer remains on the second substrate.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: May 16, 2023
    Assignee: Kioxia Corporation
    Inventors: Hidekazu Hayashi, Mie Matsuo
  • Patent number: 11579796
    Abstract: A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of ?40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of ?40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: February 14, 2023
    Assignee: Kioxia Corporation
    Inventors: Tomoya Sanuki, Yuta Aiba, Hitomi Tanaka, Masayuki Miura, Mie Matsuo, Toshio Fujisawa, Takashi Maeda
  • Publication number: 20220301599
    Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.
    Type: Application
    Filed: September 15, 2021
    Publication date: September 22, 2022
    Inventors: Tomoya SANUKI, Xu LI, Masayuki MIURA, Takayuki MIYAZAKI, Toshio FUJISAWA, Hiroto NAKAI, Hideko MUKAIDA, Mie MATSUO
  • Patent number: 11417626
    Abstract: In a manufacturing method of a semiconductor device according to an embodiment, a first substrate having a first elastic modulus is joined onto a second substrate having a second elastic modulus higher than the first elastic modulus. A first semiconductor element is formed on the first substrate. The first substrate is detached from the second substrate.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 16, 2022
    Assignee: Kioxia Corporation
    Inventors: Mie Matsuo, Hideshi Miyajima
  • Publication number: 20220251722
    Abstract: According to one embodiment, an anodization apparatus includes: a first process tank configured to perform an anodization process on a substrate; a holder configured to hold the substrate; and a first electrolyte supply system configured to supply a first electrolyte to the first process tank. The holder immerses the substrate in the first electrolyte in a state where the substrate is inclined with respect to a liquid level of the first electrolyte. The anodization process is executed in a state where the substrate is inclined with respect to the liquid level of the first electrolyte.
    Type: Application
    Filed: June 16, 2021
    Publication date: August 11, 2022
    Applicant: Kioxia Corporation
    Inventor: Mie MATSUO
  • Patent number: 11355441
    Abstract: A semiconductor device according to an embodiment includes a first substrate including a first insulating layer, a first conductive layer provided in the first insulating layer, a first metal layer provided in the first insulating layer, and a second metal layer provided between the first metal layer and the first conductive layer, a linear expansion coefficient of the second metal layer being higher than that of the first metal layer; and a second substrate including a second insulating layer, and a third metal layer provided in the second insulating layer, in contact with the first metal layer. The second substrate contacts with the first substrate.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: June 7, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kazushiro Nomura, Mie Matsuo
  • Publication number: 20220059408
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first semiconductor layer including impurity atoms with a first density, on a first substrate, forming a second semiconductor layer including impurity atoms with a second density higher than the first density, on the first semiconductor layer, and forming a porous layer resulting from porosification of at least a portion of the second semiconductor layer. The method further includes forming a first film including a device, on the porous layer, providing a second substrate provided with a second film including a device, and bonding the first and second substrates to sandwich the first and second films. The method further includes separating the first and second substrates from each other such that a first portion of the porous layer remains on the first substrate and a second portion of the porous layer remains on the second substrate.
    Type: Application
    Filed: March 10, 2021
    Publication date: February 24, 2022
    Applicant: Kioxia Corporation
    Inventors: Hidekazu HAYASHI, Mie MATSUO
  • Publication number: 20220011963
    Abstract: A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of ?40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of ?40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.
    Type: Application
    Filed: March 10, 2021
    Publication date: January 13, 2022
    Applicant: Kioxia Corporation
    Inventors: Tomoya SANUKI, Yuta AIBA, Hitomi TANAKA, Masayuki MIURA, Mie MATSUO, Toshio FUJISAWA, Takashi MAEDA
  • Patent number: 11189554
    Abstract: A semiconductor device according to the embodiments includes: a first substrate having a plurality of first through-holes; a plurality of first electrodes provided on the first substrate to be adjacent to the respective first through-holes; a plurality of second electrodes provided on the first substrate to be adjacent to the respective first through-holes and to face the respective first electrodes; and a second substrate provided to face the first substrate, the second substrate having a plurality of second through-holes facing the respective first through-holes, at least a surface of the second substrate facing the first substrate having conductivity, the second substrate being electrically connected to the second electrodes.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: November 30, 2021
    Assignee: NuFlare Technology, Inc.
    Inventors: Shiro Okada, Mie Matsuo, Hiroshi Yamashita, Shinsuke Nabeya, Kenichi Kataoka
  • Publication number: 20210343584
    Abstract: A semiconductor device manufacturing method of an embodiment includes forming a first layer in a region of a first substrate excluding an outer peripheral portion thereof; forming a first semiconductor circuit above the first layer; for a second semiconductor circuit on a second substrate; forming a second layer with a predetermined width at an outer peripheral portion of the second substrate; bonding a surface of the first substrate on a side provided with the first semiconductor circuit and a surface of the second substrate on a side provided with the second semiconductor circuit; and applying tensile stress to the first layer and the second layer to debond the first layer and the second layer, thereby forming the second substrate including the first semiconductor circuit and the second semiconductor circuit.
    Type: Application
    Filed: July 14, 2021
    Publication date: November 4, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Mie Matsuo
  • Patent number: 11101167
    Abstract: A semiconductor device manufacturing method of an embodiment includes forming a first layer in a region of a first substrate excluding an outer peripheral portion thereof; forming a first semiconductor circuit above the first layer; forming a second semiconductor circuit on a second substrate; forming a second layer with a predetermined width at an outer peripheral portion of the second substrate; bonding a surface of the first substrate on a side provided with the first semiconductor circuit and a surface of the second substrate on a side provided with the second semiconductor circuit; and applying tensile stress to the first layer and the second layer to debond the first layer and the second layer, thereby forming the second substrate including the first semiconductor circuit and the second semiconductor circuit.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 24, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Mie Matsuo
  • Publication number: 20210118898
    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
    Type: Application
    Filed: December 7, 2020
    Publication date: April 22, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Yoshiaki FUKUZUMI, Hideaki AOCHI, Mie MATSUO, Kenichiro YOSHII, Koichiro SHINDO, Kazushige KAWASAKI, Tomoya SANUKI
  • Publication number: 20210074672
    Abstract: In a manufacturing method of a semiconductor device according to an embodiment, a first substrate having a first elastic modulus is joined onto a second substrate having a second elastic modulus higher than the first elastic modulus. A first semiconductor element is formed on the first substrate. The first substrate is detached from the second substrate.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 11, 2021
    Applicant: Kioxia Corporation
    Inventors: Mie MATSUO, Hideshi MIYAJIMA
  • Patent number: 10892269
    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: January 12, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi, Mie Matsuo, Kenichiro Yoshii, Koichiro Shindo, Kazushige Kawasaki, Tomoya Sanuki
  • Publication number: 20200303241
    Abstract: A semiconductor device manufacturing method of an embodiment includes forming a first layer in a region of a first substrate excluding an outer peripheral portion thereof; forming a first semiconductor circuit above the first layer; forming a second semiconductor circuit on a second substrate; forming a second layer with a predetermined width at an outer peripheral portion of the second substrate; bonding a surface of the first substrate on a side provided with the first semiconductor circuit and a surface of the second substrate on a side provided with the second semiconductor circuit; and applying tensile stress to the first layer and the second layer to debond the first layer and the second layer, thereby forming the second substrate including the first semiconductor circuit and the second semiconductor circuit.
    Type: Application
    Filed: September 10, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Mie MATSUO