Abstract: An electronic component includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a cavity that penetrates from the first surface to the second surface of the semiconductor substrate, and an electrical mechanical element that has a movable portion formed above the first surface of the semiconductor substrate so that the movable portion is arranged above the cavity. The electronic component further includes an electric conduction plug, which penetrates from the first surface to the second surface of the semiconductor substrate, and which is electrically connected to the electrical mechanical element.

Abstract: A wafer supporting plate is formed of a glass or a resin which can permeate ultraviolet rays and has a nearly disk shape. An outer diameter of the wafer supporting plate is larger than that of the semiconductor wafer which is supported. In the wafer supporting plate, a plurality of openings are formed to correspond to plural through holes of the semiconductor wafer. The opening has an open area larger than an open area of the through hole, that is, has a larger diameter.

Abstract: A semiconductor device having a surface MEMS element, includes a semiconductor substrate, and an actuator which is arranged above the semiconductor substrate via a space and has a lower electrode, an upper electrode, and a piezoelectric layer sandwiched between the lower electrode and the upper electrode, at least an entire surface of the piezoelectric layer being substantially flat.

Abstract: A semiconductor device which is compact and thin in size, low in resistance of a current path and parasitic inductance and excellent in reliability is provided. This semiconductor device comprises a semiconductor substrate, a first main electrode which is formed on a front surface of the semiconductor substrate, a second main electrode which is formed on a rear surface of the semiconductor substrate, and a conducting portion which is formed in a direction to pierce through the semiconductor substrate, wherein the second main electrode is extracted to the front surface of the semiconductor substrate via the conducting portion. And, the conducting portion is a through via which has a through hole formed through the semiconductor substrate in its thickness direction and a conductive portion which is formed in the through hole and connected to the second main electrode.

Abstract: To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.

Abstract: Disclosed is a semiconductor device comprises a substrate, a wiring formed into a predetermined pattern above the substrate and provided with a pad portion for external connection, an interlayer insulating film formed above the substrate to cover the wiring and provided with a contact hole for a contact to a pad portion of the wiring, and a cap layer formed on the interlayer insulating film and electrically connected, via the contact hole formed in the interlayer insulating film, with the pad portion of the wiring, wherein one end portion of the cap layer is positioned at the contact hole and the cap layer is extended from the contact hole in a direction which is different from that of the pattern of the wiring.

Abstract: A semiconductor device comprises a semiconductor substrate having an through hole, a first insulation resin layer formed on an inner surface of the through hole, a second insulation resin layer formed on at least one of front and rear surfaces of the semiconductor substrate, and a first conductor layer formed in the through hole to connect at least both front and rear surfaces of the semiconductor substrate and insulated from the inner surface of the through hole with the first insulation resin layer. A second conductor layer (wiring pattern) which is electrically connected to the first conductor layer in the through hole is further provided on the second insulation resin layer. The conductor layer formed in the through hole and constituting a connecting plug has a high insulation reliability. Therefore, a semiconductor device suitable for a multi-chip package and the like can be obtained.

Abstract: Disclosed is a stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising a holding circuit holding identification information about the chip, electrically written in the chip, an identification information setting circuit setting the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked, and at least one setting terminal used to set the identification information about the chip, in the holding circuit, wherein the at least one setting terminal of any semiconductor integrated circuit chip is connected to the at least one corresponding setting terminal of any other semiconductor integrated circuit chip.

Abstract: An electronic component includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a cavity that penetrates from the first surface to the second surface of the semiconductor substrate, and an electrical mechanical element that has a movable portion formed above the first surface of the semiconductor substrate so that the movable portion is arranged above the cavity. The electronic component further includes an electric conduction plug, which penetrates from the first surface to the second surface of the semiconductor substrate, and which is electrically connected to the electrical mechanical element.

Abstract: The present invention provides an integrated circuit, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor substrate by burying an insulating material in a groove having a depth of at least 20 ?m, and a passive element formed directly or indirectly on the insulating region. It is desirable for the passive element to be an inductor.

Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.

Abstract: Disclosed is a stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising a holding circuit holding identification information about the chip, electrically written in the chip, an identification information setting circuit setting the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked, and at least one setting terminal used to set the identification information about the chip, in the holding circuit, wherein the at least one setting terminal of any semiconductor integrated circuit chip is connected to the at least one corresponding setting terminal of any other semiconductor integrated circuit chip.

Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; a plurality of diffusion layer patterns formed on the semiconductor substrate; an insulation film formed between the plural diffusion layer patterns on the semiconductor substrate; and a through plug formed to be partly surrounded by the insulation film without being in contact with the plural diffusion layer patterns and to pass through the insulation film and the semiconductor substrate. Further disclosed is a semiconductor device including: a semiconductor substrate; a plurality of diffusion layer patterns formed on the semiconductor substrate; an insulation film formed between the plural diffusion layer patterns on the semiconductor substrate; and a through plug formed to be partly surrounded by the diffusion layer pattern without being in contact with the insulation film and to pass through the diffusion layer pattern and the semiconductor substrate.

Abstract: Disclosed is a stacked type semiconductor device comprising a predetermined semiconductor integrated circuit chip and at least one semiconductor integrated circuit chip which are stacked, the at least one semiconductor integrated circuit chip including a group of circuit blocks, and the predetermined semiconductor integrated circuit chip comprising a storage section configured to store defect information indicative of a defective circuit block if the group includes the defective circuit block and a replacement circuit section configured to replace the defective circuit block.

Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.

Abstract: Disclosed is a stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising a holding circuit holding identification information about the chip, electrically written in the chip, an identification information setting circuit setting the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked, and at least one setting terminal used to set the identification information about the chip, in the holding circuit, wherein the at least one setting terminal of any semiconductor integrated circuit chip is connected to the at least one corresponding setting terminal of any other semiconductor integrated circuit chip.

Abstract: Disclosed is a stacked type semiconductor device comprising a predetermined semiconductor integrated circuit chip and at least one semiconductor integrated circuit chip which are stacked, the at least one semiconductor integrated circuit chip including a group of circuit blocks, and the predetermined semiconductor integrated circuit chip comprising a storage section configured to store defect information indicative of a defective circuit block if the group includes the defective circuit block and a replacement circuit section configured to replace the defective circuit block.

Abstract: A semiconductor device comprises an electrode formed above a substrate, an under bump metal (UBM) film on the electrode, the under bump metal film being in the shape of a recess, and a bump electrode embedded in the under bump metal film, the bump electrode having sides and bottom thereof surrounded by the under bump metal film.

Abstract: Provided is a stacked type semiconductor device formed of a plurality of semiconductor integrated circuit devices stacked, each having a specification and including a semiconductor integrated circuit chip, wherein at least three of the semiconductor integrated circuit devices are stacked in the order of a value of the specification.

Abstract: Provided a semiconductor device including: a wiring board; a semiconductor chip having a pad electrically connected to a wiring on the wiring board; a second semiconductor chip provided on the wiring board at a position facing a side of the semiconductor chip, having passive elements integrated therein, and having pads for external connection to which both ends of the passive elements are connected respectively and at least one of which is electrically connected to the wiring on the wiring board electrically connected to the pad of the semiconductor chip.