Patents by Inventor Mie Matsuo

Mie Matsuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7507634
    Abstract: To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: March 24, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Sato, Mie Matsuo, Ichiro Mizushima, Yoshitaka Tsunashima, Shinichi Takagi
  • Patent number: 7482194
    Abstract: An electronic component includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a cavity that penetrates from the first surface to the second surface of the semiconductor substrate, and an electrical mechanical element that has a movable portion formed above the first surface of the semiconductor substrate so that the movable portion is arranged above the cavity. The electronic component further includes an electric conduction plug, which penetrates from the first surface to the second surface of the semiconductor substrate, and which is electrically connected to the electrical mechanical element.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: January 27, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mie Matsuo
  • Publication number: 20090014762
    Abstract: The present invention provides a solid-state image pickup device including an image pickup pixel section which is provided on a semiconductor substrate and in which a plurality of pixels each having a photoelectric conversion element and a field-effect transistor are arranged, and a peripheral circuit section for the image pickup pixel section. An interconnect layer driving the field-effect transistor in the image pickup pixel section is formed on a first surface side of the semiconductor substrate. A light receiving surface of the photoelectric conversion element is located on a second surface side of the semiconductor substrate. The solid-state image pickup device includes a first terminal exposed from the second surface side of the semiconductor substrate, and a second terminal electrically connected to the first terminal and connectable to an external device on the first surface side of the semiconductor substrate.
    Type: Application
    Filed: July 2, 2008
    Publication date: January 15, 2009
    Inventors: Mie MATSUO, Yusuke Kohyama
  • Publication number: 20090003103
    Abstract: A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.
    Type: Application
    Filed: June 19, 2008
    Publication date: January 1, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuui SHIMIZU, Shigeo Ohshima, Mie Matsuo
  • Publication number: 20080237888
    Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.
    Type: Application
    Filed: October 31, 2007
    Publication date: October 2, 2008
    Inventors: Nobuo Hayasaka, Katsuya Okumura, Keiichi Sasaki, Mie Matsuo
  • Patent number: 7427797
    Abstract: A semiconductor device having a surface MEMS element, includes a semiconductor substrate, and an actuator which is arranged above the semiconductor substrate via a space and has a lower electrode, an upper electrode, and a piezoelectric layer sandwiched between the lower electrode and the upper electrode, at least an entire surface of the piezoelectric layer being substantially flat.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: September 23, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya Ohguro, Tamio Ikehashi, Mie Matsuo, Shuichi Sekine
  • Patent number: 7402903
    Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; a plurality of diffusion layer patterns formed on the semiconductor substrate; an insulation film formed between the plural diffusion layer patterns on the semiconductor substrate; and a through plug formed to be partly surrounded by the insulation film without being in contact with the plural diffusion layer patterns and to pass through the insulation film and the semiconductor substrate. Further disclosed is a semiconductor device including: a semiconductor substrate; a plurality of diffusion layer patterns formed on the semiconductor substrate; an insulation film formed between the plural diffusion layer patterns on the semiconductor substrate; and a through plug formed to be partly surrounded by the diffusion layer pattern without being in contact with the insulation film and to pass through the diffusion layer pattern and the semiconductor substrate.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: July 22, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mie Matsuo
  • Publication number: 20080081466
    Abstract: A method for fabricating a semiconductor device, includes forming an opening in a first film, embedding an alignment mark material for alignment with an upper layer in the opening, forming a second film on the first film in which the alignment mark material is embedded, irradiating the second film formed in a predetermined region including a position where the alignment mark material is embedded with a processing light, thereby to remove the second film to an extent that a portion of the second film remains in the predetermined region, and exposing the portion of the second film remaining in the predetermined region to an etching environment for etching the second film.
    Type: Application
    Filed: September 25, 2007
    Publication date: April 3, 2008
    Inventors: Mie MATSUO, Hisashi KANEKO
  • Patent number: 7335517
    Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: February 26, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuo Hayasaka, Katsuya Okumura, Keiichi Sasaki, Mie Matsuo
  • Publication number: 20080003771
    Abstract: To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.
    Type: Application
    Filed: June 19, 2007
    Publication date: January 3, 2008
    Inventors: Tsutomu Sato, Mie Matsuo, Ichiro Mizushima, Yoshitaka Tsunashima, Shinichi Takagi
  • Publication number: 20070254474
    Abstract: A method for manufacturing a semiconductor device includes forming a copper anti-diffusion film on a copper trench wiring layer, and forming an opening portion in the copper anti-diffusion film by laser aberration, the opening portion being formed in a region corresponding to an alignment region used for lithography process for forming an aluminum wiring on the copper trench wiring layer.
    Type: Application
    Filed: April 27, 2007
    Publication date: November 1, 2007
    Inventors: Hideo Shinomiya, Jun Hirota, Mie Matsuo, Hisashi Kaneko
  • Patent number: 7238919
    Abstract: According to an aspect of the present invention, there is provided a bonding method, comprising disposing on a first body a second body with a bump interposed therebetween; and electrically and mechanically bonding the first body and the second body with the bump by passing a heating element between the first body and the second body to melt the bump by the heating element, the heating element being heated to a melting point or more of a material configuring the bump.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: July 3, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Kaneko, Mie Matsuo, Hirokazu Ezawa
  • Patent number: 7235456
    Abstract: To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: June 26, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Sato, Mie Matsuo, Ichiro Mizushima, Yoshitaka Tsunashima, Shinichi Takagi
  • Patent number: 7177134
    Abstract: A variable-capacitance element includes: a first electrode and a second electrode which are fixed on a substrate with a spacing; a movable electrode; an actuator which is supported on a supporting portion provided on the substrate to drive the movable electrode. The movable electrode is put in an electrically connecting state with the second electrode, when the movable electrode is driven to a first position by the actuator, and the movable electrode is put in an electrically non-connected state with the second electrode, when the movable electrode is driven to a second position by the actuator. The movable electrode is constituted to be always put in an electrically non-connected state with the first electrode.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: February 13, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tamio Ikehashi, Tatsuya Ohguro, Mie Matsuo
  • Publication number: 20060209491
    Abstract: A variable-capacitance element includes: a first electrode and a second electrode which are fixed on a substrate with a spacing; a movable electrode; an actuator which is supported on a supporting portion provided on the substrate to drive the movable electrode. The movable electrode is put in an electrically connecting state with the second electrode, when the movable electrode is driven to a first position by the actuator, and the movable electrode is put in an electrically non-connected state with the second electrode, when the movable electrode is driven to a second position by the actuator. The movable electrode is constituted to be always put in an electrically non-connected state with the first electrode.
    Type: Application
    Filed: May 26, 2005
    Publication date: September 21, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tamio Ikehashi, Tatsuya Ohguro, Mie Matsuo
  • Publication number: 20060207985
    Abstract: According to an aspect of the present invention, there is provided a bonding method, comprising disposing on a first body a second body with a bump interposed therebetween; and electrically and mechanically bonding the first body and the second body with the bump by passing a heating element between the first body and the second body to melt the bump by the heating element, the heating element being heated to a melting point or more of a material configuring the bump.
    Type: Application
    Filed: February 7, 2006
    Publication date: September 21, 2006
    Inventors: Hisashi Kaneko, Mie Matsuo, Hirokazu Ezawa
  • Patent number: 7095112
    Abstract: Provided a semiconductor device including: a wiring board; a semiconductor chip having a pad electrically connected to a wiring on the wiring board; a second semiconductor chip provided on the wiring board at a position facing a side of the semiconductor chip, having passive elements integrated therein, and having pads for external connection to which both ends of the passive elements are connected respectively and at least one of which is electrically connected to the wiring on the wiring board electrically connected to the pad of the semiconductor chip.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: August 22, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuyoshi Endo, Mie Matsuo, Chiaki Takubo
  • Publication number: 20060157808
    Abstract: An electronic component includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a cavity that penetrates from the first surface to the second surface of the semiconductor substrate, and an electrical mechanical element that has a movable portion formed above the first surface of the semiconductor substrate so that the movable portion is arranged above the cavity. The electronic component further includes an electric conduction plug, which penetrates from the first surface to the second surface of the semiconductor substrate, and which is electrically connected to the electrical mechanical element.
    Type: Application
    Filed: March 17, 2006
    Publication date: July 20, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Mie Matsuo
  • Patent number: 7067897
    Abstract: A semiconductor device comprising a substrate, a plurality of dielectric films formed on the substrate, laid one upon another, and a fuse interconnect-wire formed above the substrate and covered with a predetermined one of the dielectric films, and including a fuse main body which is to be blown to electrically disconnect the fuse interconnect-wire, which is smaller than a bottom of a fuse-blowing recess made in the predetermined dielectric film, which has a length not less than the diameter of a fuse-blowing laser beam and which opposes the bottom of the fuse-blowing recess.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: June 27, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaaki Hatano, Hiroshi Ikegami, Takamasa Usui, Mie Matsuo
  • Publication number: 20060131651
    Abstract: To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.
    Type: Application
    Filed: January 27, 2006
    Publication date: June 22, 2006
    Inventors: Tsutomu Sato, Mie Matsuo, Ichiro Mizushima, Yoshitaka Tsunashima, Shinichi Takagi