Patents by Inventor Mie Matsuo

Mie Matsuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6709966
    Abstract: A semiconductor device comprising the bump containing magnetic body, magnetic body, the bump including non-magnetic body for at least partially covering the magnetic body, mixture of magnetic particles and non-magnetic particles and the bump including baked magnetic particles and baked non-magnetic particles.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: March 23, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshimi Hisatsune, Keiichi Sasaki, Hiroshi Ikegami, Mie Matsuo, Nobuo Hayasaka, Katsuya Okumura
  • Publication number: 20040038520
    Abstract: A method of manufacturing a semiconductor device according to a first aspect of the present invention includes: forming a first photosensitive resin cured layer including a first opening above a semiconductor substrate, on which a underlying wiring layer is formed, the first opening being made above the underlying wiring layer; forming a second photosensitive resin cured layer including a second opening on the first photosensitive resin cured layer, a bottom of the second opening including an opening top of the first opening; and forming a wiring layer so as to fill in the first and second openings.
    Type: Application
    Filed: March 24, 2003
    Publication date: February 26, 2004
    Inventors: Masaharu Seto, Mie Matsuo
  • Publication number: 20030230803
    Abstract: Disclosed is a semiconductor device comprises a substrate, a wiring formed into a predetermined pattern above the substrate and provided with a pad portion for external connection, an interlayer insulating film formed above the substrate to cover the wiring and provided with a contact hole for a contact to a pad portion of the wiring, and a cap layer formed on the interlayer insulating film and electrically connected, via the contact hole formed in the interlayer insulating film, with the pad portion of the wiring, wherein one end portion of the cap layer is positioned at the contact hole and the cap layer is extended from the contact hole in a direction which is different from that of the pattern of the wiring.
    Type: Application
    Filed: June 10, 2003
    Publication date: December 18, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Mie Matsuo
  • Patent number: 6614106
    Abstract: A stacked circuit device comprises a base substrate having a terminal, an interposer arranged on the base substrate and formed of a semiconductor substrate, the interposer having a first terminal connected to the terminal of the base substrate, a second terminal, and a circuit coupled to the second terminal and including an active element, and an integrated circuit chip arranged on the interposer and having a terminal connected to the second terminal.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: September 2, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Nobuo Hayasaka
  • Publication number: 20030155590
    Abstract: A semiconductor device comprising a substrate, a plurality of dielectric films formed on the substrate, laid one upon another, and a fuse interconnect-wire formed above the substrate and covered with a predetermined one of the dielectric films, and including a fuse main body which is to be blown to electrically disconnect the fuse interconnect-wire, which is smaller than a bottom of a fuse-blowing recess made in the predetermined dielectric film, which has a length not less than the diameter of a fuse-blowing laser beam and which opposes the bottom of the fuse-blowing recess.
    Type: Application
    Filed: February 13, 2003
    Publication date: August 21, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaaki Hatano, Hiroshi Ikegami, Takamasa Usui, Mie Matsuo
  • Publication number: 20030067052
    Abstract: The present invention provides an integrated circuit, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor substrate by burying an insulating material in a groove having a depth of at least 20 &mgr;m, and a passive element formed directly or indirectly on the insulating region. It is desirable for the passive element to be an inductor.
    Type: Application
    Filed: November 18, 2002
    Publication date: April 10, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Nobuo Hayasaka, Noriaki Matsunaga, Katsuya Okumura
  • Publication number: 20030062612
    Abstract: Disclosed is a stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising a holding circuit holding identification information about the chip, electrically written in the chip, an identification information setting circuit setting the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked, and at least one setting terminal used to set the identification information about the chip, in the holding circuit, wherein the at least one setting terminal of any semiconductor integrated circuit chip is connected to the at least one corresponding setting terminal of any other semiconductor integrated circuit chip.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 3, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mie Matsuo, Kenichi Imamiya
  • Publication number: 20030052409
    Abstract: A semiconductor device comprises an electrode formed above a substrate, an under bump metal (UBM) film on the electrode, the under bump metal film being in the shape of a recess, and a bump electrode embedded in the under bump metal film, the bump electrode having sides and bottom thereof surrounded by the under bump metal film.
    Type: Application
    Filed: August 27, 2002
    Publication date: March 20, 2003
    Inventors: Mie Matsuo, Masahiro Miyata, Hirokazu Ezawa
  • Patent number: 6504227
    Abstract: The present invention provides an integrated circuit, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor substrate by burying an insulating material in a groove having a depth of at least 20 &mgr;m, and a passive element formed directly or indirectly on the insulating region. It is desirable for the passive element to be an inductor.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: January 7, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Nobuo Hayasaka, Noriaki Matsunaga, Katsuya Okumura
  • Publication number: 20020143656
    Abstract: There is provided a method for trading electronic products by transmitting/receiving electronic data by way of a communication network, the method comprising prompting an expected buyer of an electronic product to input a specification of the electronic product the expected buyer wants to buy, extracting the electronic product which meets the specification of the electronic product from a database, and outputting information of the electronic product to a manufacturer.
    Type: Application
    Filed: March 8, 2002
    Publication date: October 3, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mie Matsuo, Nobuo Hayasaka
  • Publication number: 20020036340
    Abstract: A stacked circuit device comprises a base substrate having a terminal, an interposer arranged on the base substrate and formed of a semiconductor substrate, the interposer having a first terminal connected to the terminal of the base substrate, a second terminal, and a circuit coupled to the second terminal and including an active element, and an integrated circuit chip arranged on the interposer and having a terminal connected to the second terminal.
    Type: Application
    Filed: September 21, 2001
    Publication date: March 28, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Nobuo Hayasaka
  • Publication number: 20020036338
    Abstract: Provided is a stacked type semiconductor device formed of a plurality of semiconductor integrated circuit devices stacked, each having a specification and including a semiconductor integrated circuit chip, wherein at least three of the semiconductor integrated circuit devices are stacked in the order of a value of the specification.
    Type: Application
    Filed: September 25, 2001
    Publication date: March 28, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mie Matsuo, Nobuo Hayasaka, Tsunetoshi Arikado, Hidemi Ishiuchi, Koji Sakui, Chiaki Takubo
  • Patent number: 5775980
    Abstract: This invention provides a polishing method including the steps of forming a film to be polished on a substrate having a recessed portion in its surface so as to fill at least the recessed portion, and selectively leaving the film to be polished behind in the recessed portion by polishing the film by using a polishing agent containing polishing particles and a solvent, and having a pH of 7.5 or more. The invention also provides a polishing apparatus including a polishing agent storage vessel for storing a polishing agent, a turntable for polishing an object to be polished, a polishing agent supply pipe for supplying the polishing agent from the polishing agent storage vessel onto the turntable, a polishing object holding jig for holding the object to be polished such that the surface to be polished of the object opposes the turntable, and a polishing agent supply pipe temperature adjusting unit, connected to the polishing agent supply pipe, for adjusting the temperature of the polishing agent.
    Type: Grant
    Filed: November 4, 1996
    Date of Patent: July 7, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasutaka Sasaki, Mie Matsuo, Rempei Nakata, Junichi Wada, Nobuo Hayasaka, Hiroyuki Yano, Haruo Okano
  • Patent number: 5731634
    Abstract: The present invention provides a method of manufacturing a semiconductor device, including the steps of forming a metal oxide film made of a metal oxide having a decrease in standard free energy smaller than a decrease in standard free energy of hydrogen oxide or of carbon oxide, on an insulating film formed on a semiconductor substrate, forming a metal oxide film pattern by subjecting a treatment to the metal oxide film, and converting said metal oxide pattern into at least one of an electrode and a wiring made of a metal which is a main component constituting the metal oxide, by reducing the metal oxide film pattern at a temperature of 80.degree. to 500.degree. C.
    Type: Grant
    Filed: June 6, 1996
    Date of Patent: March 24, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Haruo Okano, Nobuo Hayasaka, Kyoichi Suguro, Hideshi Miyajima, Jun-ichi Wada
  • Patent number: 5607718
    Abstract: This invention provides a polishing method including the steps of forming a film to be polished on a substrate having a recessed portion in its surface so as to fill at least the recessed portion, and selectively leaving the film to be polished behind in the recessed portion by polishing the film by using a polishing agent containing polishing particles and a solvent, and having a pH of 7.5 or more. The invention also provides a polishing apparatus including a polishing agent storage vessel for storing a polishing agent, a turntable for polishing an object to be polished, a polishing agent supply pipe for supplying the polishing agent from the polishing agent storage vessel onto the turntable, a polishing object holding jig for holding the object to be polished such that the surface to be polished of the object opposes the turntable, and a polishing agent supply pipe temperature adjusting unit, connected to the polishing agent supply pipe, for adjusting the temperature of the polishing agent.
    Type: Grant
    Filed: September 2, 1994
    Date of Patent: March 4, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasutaka Sasaki, Mie Matsuo, Rempei Nakata, Junichi Wada, Nobuo Hayasaka, Hiroyuki Yano, Haruo Okano
  • Patent number: 5561082
    Abstract: The present invention provides a method of manufacturing a semiconductor device, including the steps of forming a metal oxide film made of a metal oxide having a decrease in standard free energy smaller than a decrease in standard free energy of hydrogen oxide or of carbon oxide, on an insulating film formed on a semiconductor substrate, forming a metal oxide film pattern by subjecting a treatment to the metal oxide film, and converting said metal oxide pattern into at least one of an electrode and a wiring made of a metal which is a main component constituting the metal oxide, by reducing the metal oxide film pattern at a temperature of 80.degree. to 500.degree. C.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: October 1, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Haruo Okano, Nobuo Hayasaka, Kyoichi Suguro, Hideshi Miyajima, Jun-ichi Wada
  • Patent number: 5424246
    Abstract: According to this invention, there is provided a method of forming a groove wiring layer, including the steps of forming a metal oxide film, consisting of a metal oxide having a decrease in standard free energy smaller than a decrease in standard free energy of a hydrogen oxide or of a carbon oxide, on an insulating film formed on a semiconductor substrate, and reducing the metal oxide film to form an electrode-wiring layer consisting of a metal which is a main component constituting the metal oxide. In this manner, an electrode-wiring layer having high EM and SM resistances without causing an increase in electric resistivity caused by an impurity or the like can be obtained.
    Type: Grant
    Filed: July 30, 1993
    Date of Patent: June 13, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Haruo Okano, Nobuo Hayasaka, Kyoichi Suguro, Hideshi Miyajima, Jun-ichi Wada