Abstract: A flash memory device according to the present invention comprises: a memory cell array having a plurality of memory cells; a dummy cell array having a plurality of dummy cells and connected to each word line of the memory cell array; a means for applying a voltage to a bit line of the dummy cell array; a level detector for detecting potential of the bit line in the dummy cell array; a row decoder for selecting a word line of the dummy cell array and the memory cell array according to an address signal; and a column decoder for selecting a bit line of the memory cell array according to the address signal; a sense amplifier enabled by an output of the level detector and for comparing data stored on the cell of the memory cell array with data stored on a reference cell.

Abstract: The present invention discloses a method and circuit for driving a word line and a bit line for a read/write operation of a quad data rate synchronous semiconductor memory device which can perform the read/write operation in one cycle in the QDR device in which the read and write operations are individually performed in a double data rate (DDR) type, and which can read data in a burst length according to one address variation by using a prefetched method in the read operation. The method for driving the quad data rate synchronous semiconductor memory device includes the steps of: enabling a word line for a read operation by being synchronized with a rising edge of one clock cycle, and disabling word line and bit line select signals for the read operation before a falling edge; and enabling a word line for a write operation by being synchronized with the falling edge of the clock cycle, and disabling word line and bit line select signals for the write operation before a rising edge of a succeeding clock cycle.

Abstract: A raw panel for a liquid crystal display. A first substrate includes first electrodes opposing a second substrate including second electrodes. A plurality of main walls having a predetermined height are arranged in a striped pattern between first and second substrates to define a plurality of channels. The channels include sets of pixels, each set formed by three neighboring channels. First sub-walls are mounted at a predetermined distance from a first end line and between the main walls defining first channels in sets the first channels each having at least two separate spaces. Second sub-walls are mounted at a predetermined second distance from the first end line and between the main walls defining second channels in sets, the second channels each having at least two separate spaces. The raw panel is opened at the first end line and at a second end line opposite the first end line.

Abstract: There is provided a method of driving a cholesteric liquid crystal display (LCD) panel by sequentially applying a selection line voltage to individual scan electrode lines and simultaneously applying data signals to all data electrode lines in order to selecting a state of each cholesteric liquid crystal cell according to a given gray scale level. Each selection time, during which the selection line voltage is applied to a certain scan electrode line and simultaneously the data signals are applied to all of the data electrode lines, is constant. Each selection time is divided into a first part time and a second part time. A low selection line voltage is applied to a relevant scan electrode line during the first part time. A high selection line voltage having a different level from the low selection line voltage is applied to the relevant scan electrode line during the second part time.

Abstract: There is disclosed a code addressable memory (“CAM”) cell in a flash memory device. In order to stabilize the operation of the CAM cell in a flash memory device operating at a low voltage, the present invention manufactures a CAM cell in which a floating gate is formed to extend on more than two active regions and more than two cell arrays are connected in parallel commonly using a source region and a drain region. Therefore, the present invention can increase the gate-coupling ration of the CAM cell, thus stabilizing the operation of the CAM cell at a device for low-voltage use.

Abstract: A flash memory device according to the present invention comprises: a memory cell array having a plurality of memory cells; a dummy cell array having a plurality of dummy cells and connected to each word line of the memory cell array; a loading means for applying a voltage to a bit line of the dummy cell array; a level detector for detecting potential of the bit line in the dummy cell array; a row decoder for selecting a word line of the dummy cell array and the memory cell array according to an address signal; and a column decoder for selecting a bit line of the memory cell array according to the address signal; a sense amplifier enabled by an output of the level detector and for comparing a data stored on the cell of the memory cell array with a data stored on a reference cell.

Abstract: A flash memory device includes a plurality of banks having a memory cell array and a row and column decoder, a system for classifying an input address into a read address and a write address depending on read or write operation, a first selecting system for enabling one of the plurality of the banks depending on the bank address allocated to the input address and the read address to perform the read operation, a second selecting system for enabling one of the plurality of the banks depending on the bank address allocated to the input address and the write address to perform the write operation, a sense amplifier for sensing data of the bank to compare them with data of a reference cell, and a pumping system for supplying a given bias to the bank.

Abstract: A method of transmitting data in a system including at least one data channel and a separate clock channel is disclosed. The method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal has been generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a front edge and a back edge, and the data signal is modulated onto the clock signal by moving at least one edge (i.e. front or back or both) of the plurality of pulses, thereby to create a combined clock and data signal.

Abstract: The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a return channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock & data signal provided by the transmitter.

Abstract: There is provided a circuit for sensing a memory cell. The circuit includes a main cell, a reference cell, a first loading unit for providing a preset voltage to a sensing node of the main cell, a second loading unit for supplying a prescribed voltage to a sensing node of the reference cell, a first switching unit for adjusting the potential of the main cell sensing node, a second switching unit for controlling the potential of the reference cell sensing node, a first voltage controlling unit for adjusting the potential of a bit line of the main cell, a second voltage controlling unit for adjusting the potential of a bit line of the reference cell, and a sense amplifier for sensing a state of the main cell by comparing the potential of the main cell sensing node and that of the reference cell sensing node.

Abstract: The present invention discloses a method and circuit for driving a word line and a bit line for a read/write operation of a quad data rate synchronous semiconductor memory device which can perform the read/write operation in one cycle in the QDR device in which the read and write operations are individually performed in a double data rate (DDR) type, and which can read data in a burst length according to one address variation by using a prefetched method in the read operation. The method for driving the quad data rate synchronous semiconductor memory device includes the steps of: enabling a word line for a read operation by being synchronized with a rising edge of one clock cycle, and disabling word line and bit line select signals for the read operation before a falling edge; and enabling a word line for a write operation by being synchronized with the falling edge of the clock cycle, and disabling word line and bit line select signals for the write operation before a rising edge of a succeeding clock cycle.

Abstract: There is disclosed a method of programming a flash memory cell, which is performed applying a given voltage a gate and a drain and maintaining a source and a substrate at a ground potential. The method variably applies a given voltage, with two or more steps, to one of the gate and drain terminals while applying a given voltage to the other of the gate and drain terminals, thus reducing the programming current per cell. Accordingly, the present invention can improve reliability and throughput of the flash memory cell.

Abstract: An address buffer in a flash memory includes a buffer section for buffering external addresses to select specific sectors in the flash memory, a code storage section for storing a code to select a memory sector in the flash memory, a setting section for outputting internal addresses IA17˜IA17 selecting the memory sector, by using the code outputted from the code storage section and sector select addresses among the external addresses.

Abstract: A high speed block matching algorithm for a bi-directional motion vector estimation, capable of improving the accuracy and the amount of computation in the bi-directional motion vector estimation by using a uniform motion model for displacement and spatial correlation of motion vectors in a bi-directional motion estimated prediction structure adaptively using pictures forwardly predicted from a past reference picture and pictures bi-directionally predicted from two, past and future reference.