Abstract: A method of transmitting data in a system including at least one data channel and a separate clock channel is disclosed. The method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal has been generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a front edge and a back edge, and the data signal is modulated onto the clock signal by moving at least one edge (i.e. front or back or both) of the plurality of pulses, thereby to create a combined clock and data signal.

Abstract: A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver.

Abstract: A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver.

Abstract: An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The differential amplifier pair receives differential data signal pairs from each of a transmission line and a transmitter. The output circuitry receives signals from the differential amplifier pair and, in response, forms single-ended output logic signals. The output amplifier suppresses electronic input noise throughput using an asymmetric transfer characteristic that offsets output signal logic levels with respect to input noise signal levels. The asymmetric transfer characteristic is produced by skewing a transfer characteristic of the differential amplifier pair using an asymmetrical transistor configuration at an output side of the differential amplifier pair.

Abstract: The present invention relates to new aziridine derivative that is represented by following general chemical formulae (la) or (lb), and to their preparation method. In the above mentioned chemical formulae, R2 and R3 can be same or different, and they are hydrogen, low-quality alkyl or cycloalkyl respectively; R4 can be selected among hydrogen, alkyl, aril, or amino protective group, and amino protective group is, for example, (PH)3C, FMOC (9-fluorenylmethyl oxycarbonyl), alkoxycarbonyl, ariloxycarbonyl, aralkyloxycarbonyl and R5CO, R5SO2 where R5 is alkyl or aril or aralkyl.

Abstract: A scheme for reducing jitter in high-speed digital communication by adaptively controlling the loop bandwidth of a receiver PLL to reduce the relative jitter between the recovered data and clock. The scheme uses phase pointer activity to represent the relative jitter. The phase pointer activity is measured and used to control the receiver PLL loop bandwidth. The receiver PLL loop bandwidth is repeatedly incremented or decremented by a step size based on the comparison between a newly measured activity value and the old activity value, until the phase pointer activity reaches a minimum. Because the PLL performance requirement of the transmitter can be relaxed, compatibility with legacy transmitters and multi-vendor transmitters is enhanced. Because tight control of fabrication process parameters of PLLs may be relaxed, the fabrication yield may also be improved.

Abstract: Logic gates are provided that include a diode-connected metal-oxide-semiconductor field-effect transistor (MOSFET) to produce a gate threshold voltage that differs from a mid-supply voltage level, while providing symmetry in the switching transients of the output logic signals. In one embodiment, the logic gate is a NAND gate. Use of a diode-connected n-type MOSFET in a ground path produces a threshold voltage level higher than the mid-supply voltage level. Use of a diode-connected p-type MOSFET in a supply voltage path produces a threshold voltage level lower than the mid-supply voltage level. In another embodiment, the logic gate is a NOR gate. Use of a diode-connected n-type MOSFET in a ground path produces a threshold voltage level higher than the mid-supply voltage level. Use of a diode-connected p-type MOSFET in a supply voltage path produces a threshold voltage level lower than the mid-supply voltage level.

Abstract: The present invention relates to a new aziridine derivative that is represented herein by general chemical formulae (Ia) or (Ib), and to their preparation method. In the said chemical formulae, R2 and R3 can be the same or different, and they are hydrogen, low-quality alkyl or cycloalkyl respectively; R4 can be selected among hydrogen, alkyl, aryl, or amino protective group; and amino protective group is, for example, (Ph)3C, and FMOC(9-fluorenylmethyloxycarbonyl), alkoxycarbonyl, aryloxycarbonyl, aralkyloxycarbonyl and R5CO, R5SO2 where R5 is alkyl, aryl or aralkyl.

Abstract: Provided are a method of manufacturing a plastic substrate having a TFT, a substrate manufactured thereby, a method of manufacturing a flat panel display device, and a flat display device manufactured thereby, which can be used for a flexible flat display device. The method includes: preparing a film in which a plurality of conductive patterns are included; bonding the film to a substrate; forming the TFT in a manner such that it is electrically connected to the conductive pattern on the film; and forming an insulating layer covering the TFT on the film.

Abstract: A semiconductor device that initializes memory cells of an activated wordline group is provided. The device includes: a control signal generation circuit, which generates first and second control signals based on an activated setting signal and an initial data value during an initial value setting operation; a first power supply circuit, which supplies power to bitlines in response to the first control signal; a second power supply circuit, which supplies power to complementary bitlines in response to the second control signal; a plurality of wordlines connected to respective memory cells; and a row decoder, which selects a group of wordlines from among the plurality of wordlines based on the setting signal and a selection address and simultaneously activates the selected group of wordlines.

Abstract: An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The differential amplifier pair receives differential data signal pairs from each of a transmission line and a transmitter. The output circuitry receives signals from the differential amplifier pair and, in response, forms single-ended output logic signals. The output amplifier suppresses electronic input noise throughput using an asymmetric transfer characteristic that offsets output signal logic levels with respect to input noise signal levels. The asymmetric transfer characteristic is produced by skewing a transfer characteristic of the differential amplifier pair using an asymmetrical transistor configuration at an output side of the differential amplifier pair.

Abstract: There is provided a method of driving a cholesteric liquid crystal display (LCD) panel by sequentially applying a selection line voltage to individual scan electrode lines and simultaneously applying data signals to all data electrode lines in order to select a state of each cholesteric liquid crystal cell according to a given gray scale level. Each selection time, during which the selection line voltage is applied to a certain scan electrode line and simultaneously the data signals are applied to all of the data electrode lines, is constant. Each selection time is divided into a first part time and a second part time. A low selection line voltage is applied to a relevant scan electrode line during the first part time. A high selection line voltage having a level different from that of the low selection line voltage is applied to the relevant scan electrode line during the second part time.

Abstract: The present invention relates to a serial interface transmission system with more than one data line, in which the transmitted data has in-band and out-of-band characters. More particularly, the present invention relates to methods and systems for sending side channel data over a high-speed digital communications link, e.g., a video link. One embodiment of the invention provides a high-speed digital transmitter capable of sending side channel data. The transmitter includes a channel zero encoder, a multiplexer, data enable out (DEout) control logic, and a channel one encoder. The channel one encoder receives input from the channel one multiplexer and the channel one DEout control logic. Another embodiment of the invention provides a high-speed digital receiver capable of receiving side channel data. The receiver includes a channel zero decoder, a channel one decoder, DEI signal and FIFO control signal recovery logic, and a channel one de-multiplexer.

Abstract: A system and method for measuring and utilizing a pseudo pixel error rate in digital data transmission is disclosed. As an alternative to measuring actual pixel error rate measurement, the present invention uses a pseudo pixel error rate detection scheme where the errors occurred in the special character patterns used in data encoding are measured. A particular embodiment uses a de-glitch filter for filtering the glitches from an unfiltered data enable (DE), a delay for delaying the unfiltered DE to match the delay of the de-glitch filter, and a comparator for comparing the unfiltered DE and the filtered DE to determine the occurrence of an error. It further includes a counter to count the errors occurred.

Abstract: A serial data transmission system in which a transmitter encodes data in accordance with a TMDS-like encoding algorithm and transmits the TMDS-like encoded data over a serial link to a receiver. The encoded data are transmitted as a run length limited (“RLL”) code word sequence, including transition-minimized code words. In some embodiments, the RLL code word sequence includes only Min words, including both DC balancing Min words and DC unbalancing Min words. In other embodiments, the RLL code word sequence includes both transition-maximized code words and transition-minimized code words. Other aspects of the invention are circuitry and methods for TMDS-like encoding of data for transmission as an RLL code word sequence.

Abstract: Provided are a memory controller that selectively changes a frequency of a memory clock signal, a smart card including the memory controller, and a method of controlling a read operation of a memory. The memory controller includes a central processing unit (CPU), a memory interface, and a frequency change controller. The CPU outputs a read command signal in response to a data read request signal and outputs a write command signal in response to a data write request signal. The memory interface outputs a plurality of control signals in response to one of the read command signal and the write command signal, generates a memory clock signal based on a system clock signal, and changes a frequency of the memory clock signal in response to a frequency change control signal. The frequency change controller outputs the frequency change control signal in response to the plurality of control signals and the memory clock signal.

Abstract: Additional information on the phase of an external clock signal is obtained by using clock signals to determine if a phase difference between an external clock signal and a first internal sampling clock signal is less than a pre-selected value. If the system determines that the phase difference is less than a pre-selected value, one embodiment samples the incoming data with a second internal sampling clock signal, having a selected phase relationship to the first internal sampling clock signal, such as ½ a clock period out of phase. By maintaining sufficient phase difference between the active edge of the external clock and the active edge of the internal sampling clock, the embodiment provides a sufficient setup/hold margin to avoid a metastability or other problem in a subsystem receiving data across an asynchronous boundary.

Abstract: A raw panel for a liquid crystal display. A first substrate includes first electrodes opposing a second substrate including second electrodes. A plurality of main walls having a predetermined height are arranged in a striped pattern between first and second substrates to define a plurality of channels. The channels include sets of pixels, each set formed by three neighboring channels. First sub-walls are mounted at a predetermined distance from a first end line and between the main walls defining first channels in sets the first channels each having at least two separate spaces. Second sub-walls are mounted at a predetermined second distance from the first end line and between the main walls defining second channels in sets, the second channels each having at least two separate spaces. The raw panel is opened at the first end line and at a second end line opposite the first end line.

Abstract: The present invention relates to a new aziridine derivative that is represented herein by general chemical formulae (Ia) or (Ib), and to their preparation method. In the said chemical formulae, R2 and R3 can be the same or different, and they are hydrogen, low-quality alkyl or cycloalkyl respectively; R4 can be selected among hydrogen, alkyl, aryl, or amino protective group; and amino protective group is, for example, (Ph)3C, and FMOC(9-fluorenylmethyloxycarbonyl), alkoxycarbonyl, aryloxycarbonyl, aralkyloxycarbonyl and R5CO, R5SO2 where R5 is alkyl, aryl or aralkyl.

Abstract: A circuit for sensing a memory cell includes a main cell, a reference cell, a first loading unit for providing a preset voltage to a sensing node of the main cell, a second loading unit for supplying a prescribed voltage to a sensing node of the reference cell, a first switching unit for adjusting the potential of the main cell sensing node, a second switching unit for controlling the potential of the reference cell sensing node, a first voltage controlling unit for adjusting the potential of a bit line of the main cell, a second voltage controlling unit for adjusting the potential of a bit line of the reference cell, and a sense amplifier for sensing a state of the main cell by comparing the potential of the main cell sensing node and that of the reference cell sensing node.