Abstract: The invention provides a left-right parallel loop bipolar electrode. At its front-section part, a metal sleeve and a rigid tube are arranged in parallel at an interval on left and right, two insulating tubes are fixed at heads of the metal sleeve and the rigid tube respectively, one end of a positive electrode is connected with a wire, led from the rigid tube, with an insulating layer in the corresponding insulating tube, and another wire with an insulating layer is welded with the metal sleeve. At its rear-section part, a tail end of the metal straight tube is connected with a binding post, the binding post is connected with a double-core wire, and the two wires with the insulating layers penetrate through the metal straight tube to be correspondingly connected with the double-core wire respectively; the other end of the positive electrode is fixed in the other insulating tube.

Abstract: A diisononyl terephthalate (DINT) plasticizer is synthesized by esterifying an isononanol mixture composed of multiple alcohols with pure terephthalic acid in the presence of an esterification catalyst, and the DINT plasticizer due to featuring a low plasticizer migration below 1.4% and a low glass transition temperature below ?75° C. is so suitable for making those soft plastic products, such as hoses, wires, cables, exercise mats, table mats, playing balls or disposable gloves, required for having a high content of plasticizers more than 70 PHR.

Abstract: Techniques are described for decoding a message. In one example, the techniques include obtaining a first message comprising a plurality of information bits and a plurality of parity bits, decoding the first message using an iterative decoding algorithm to generate a first bit sequence, generating a miscorrection metric based at least on the first bit sequence and one or more reliability values corresponding to one or more bits in the first message, determining whether a miscorrection happened in the decoder by comparing the miscorrection metric with a first threshold, and upon determining that a miscorrection did not happen, outputting the first bit sequence as a decoded message.

Abstract: A pressure sensor comprises a first substrate and a cap attached to the first substrate. The cap includes a processing circuit, a cavity and a deformable membrane separating the cavity and a port open to an outside of the pressure sensor. Sensing means are provided for converting a response of the deformable membrane to pressure at the port into a signal capable of being processed by the processing circuit. The cap is attached to the first substrate such that the deformable membrane faces the first substrate and such that a gap is provided between the deformable membrane and the first substrate which gap contributes to the port. The first substrate comprises a support portion the cap is attached to, a contact portion for electrically connecting the pressure sensor to an external device, and one or more suspension elements for suspending the support portion from the contact portion.

Abstract: Techniques are described for decoding a codeword, including, obtaining a first message comprising a plurality of information bits and a plurality of parity bits, wherein the message corresponds to a turbo product code (TPC) comprising two or more constituent codes, wherein each constituent code corresponds to a class of error correcting codes capable of correcting a pre-determined number of errors, performing an iterative TPC decoding using at least one of a first decoder corresponding to a first constituent code and a second decoder corresponding to a second constituent code on the first message to generate a second message, determining if the decoding was successful. Upon determining that the TPC decoding was not successful, determining one or more error locations in the second message based on a third constituent code using a third decoder. The third decoder determines the one or more error locations in a predetermined number of clock cycles.

Abstract: A heat dissipation device includes a housing and a heat pipe. The heat pipe has an open end, which is inserted into an opening on a top side of the housing, such that a heat pipe chamber of the heat pipe is communicated with a housing chamber of the housing and an extended portion extended from the open end of the heat pipe is pressed against a bottom side of the housing, as well as a heat pipe wick structure of the heat pipe is connected to a housing wick structure of the housing, so as to increase heat transfer effect.

Abstract: Disclosed are a compressive sensing system based on a personalized basis and a method thereof; first a sensing end senses an original signal and transmits the original signal to a reconstruction end; the reconstruction end generates a personalized basis by means of a dictionary learning method; next, the sensing end is made to sample the original signal according to a sampling matrix to generate a compressed signal and transmit the compressed signal to the reconstruction end, so that the reconstruction end executes a compressive sensing reconstruction algorithm according to the personalized basis and the compressed signal to recover the compressed signal into the original signal, thereby achieving an effect of improving signal recovering quality and a compression ratio.

Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 ?m to 750 ?m, and the wall surface of the dam element surrounding the sensing area is a rough surface.

Abstract: An integrated circuit (IC) die for electromagnetic band gap (EBG) noise suppression is provided. A power mesh and a ground mesh are stacked within a back end of line (BEOL) region overlying a semiconductor substrate, and an inductor is arranged over the power and ground meshes. The inductor comprises a plurality of inductor segments stacked upon one another and connected end to end to define a length of the inductor. A capacitor underlies the power and ground meshes, and is connected in series with the inductor. Respective terminals of the capacitor and the inductor are respectively coupled to the power and ground meshes. A method for manufacturing the IC die is also provided.

Abstract: The present invention relates to a full-Si molecular sieve, wherein the full-Si molecular sieve has a Q4/Q3 of (10-90):1 wherein Q4 is the peak strength at the chemical shift of ?112±2 ppm in the 29Si NMR spectrum of the full-Si molecular sieve, expressed as the peak height relative to the base line; and Q3 is the peak strength at the chemical shift of ?103±2 ppm in the 29Si NMR spectrum of the full-Si molecular sieve, expressed as the peak height relative to the base line.

Abstract: Some embodiments relate to multiple MEMS devices that are integrated together on a single substrate. A device substrate comprising first and second micro-electro mechanical system (MEMS) devices is bonded to a capping structure. The capping structure comprises a first cavity arranged over the first MEMS device and a second cavity arranged over the second MEMS device. The first cavity is filled with a first gas at a first gas pressure. The second cavity is filled with a second gas at a second gas pressure, which is different from the first gas pressure. A recess is arranged within a lower surface of the capping structure. The recess abuts the second cavity. A vent is arranged within the capping structure. The vent extends from a top of the recess to the upper surface of the capping structure. A lid is arranged within the vent and configured to seal the second cavity.

Abstract: Systems, methods, architectures, and computer program products for linking multiple devices are disclosed. In an example for linking a mobile device with a desktop device, an identifier of a mobile device can be received from a desktop computer. The identifier can be used to send a link to the mobile device. When the link is accessed, a code and a channel are generated. The mobile device is connected to the channel and the code is provided to the mobile device. The code is entered at the desktop device and the desktop device is connected to the channel responsive to the code being validated, thereby linking the desktop and mobile devices.

Abstract: A light emitting diode (LED) packaging structure including a metal pad, an electric static discharge (ESD) protection element and an LED chip is provided. The metal pad has a first pad portion having a first top surface with a first concave configured thereon and a second pad portion having a second top surface with a second concave configured thereon. The ESD protection element has two first electrode portions respectively configured in the first concave and the second concave. The LED chip is located above the ESD protection element and has two second electrode portions respectively configured on the first top surface and the second top surface. A frame and a light emitting device having the frame that both include the above LED packaging structure are described herein. A light emitting device having an omni-directional light emitting effect is also described and includes the above LED packaging structure.

Abstract: An electrode structure of a transistor, and a pixel structure and a display apparatus comprising the electrode structure of the transistor are disclosed. The electrode structure of the transistor comprises a first electrode and a second electrode. The first electrode has at least two first portions and at least one second portion. The first portions are substantially parallel with each other and each has a first width. The second portion has a second width, and connects the substantially parallel first portions to define a space with an opening. The first width is substantially greater than the second width.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract: A semiconductor device includes a device substrate and a conductive capping substrate. The device substrate includes at least one micro-electro mechanical system (MEMS) device. The conductive capping substrate is bonded to the device substrate and includes a cap portion covering the MEMS device, and a conductor portion in electrical contact with the device substrate.

Abstract: A method and apparatus for applying DF processing and SAO processing to reconstructed video data are disclosed. The DF processing is applied to a current access element of reconstructed video data to generate DF output data and the deblocking status is determined while applying the DF processing. Status-dependent SAO processing is applied to one or more pixels of the DF output data according to the deblocking status. The status-dependent SAO processing comprises SAO processing, partial SAO processing, and no SAO processing. The SAO starting time for SAO processing is between the DF-output starting time and ending time for the current block. The DF starting time of a next block can be earlier than the SAO ending time of the current block by a period oft, where t is smaller than time difference between the DF-output starting time and the DF starting time of the next block.

Abstract: A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

Abstract: A lamp includes a substrate having a center region and a peripheral region, a first subset of light-emitting devices disposed on the center region, and a second subset of light-emitting devices disposed on the peripheral region. A temperature difference between the center region and the peripheral region is greater than 10 degrees.