Abstract: Disclosed is a battery pack in which a seating recess is provided in a horizontal frame so that connection members pass through the horizontal frame through the seating recess, thereby maximizing a height of the horizontal frame. A vertical frame cover is provided in a vertical frame to secure a height of the vertical frame side in each module space. A sealing member is provided in the seating recess to seal the seating recess. A double shielding structure, including a module space cover shielding each module space and a battery pack cover shielding a battery pack housing as a whole, is provided to maximize airtightness of the battery pack.

Abstract: A road side unit (RSU) device for vehicle-to-everything (V2X) service can transmit, to a V2X server, a message for configuring an RSU subscription area for a V2X service; receive, from the V2X server, at least one first V2X message published by at least one first V2X device associated with the RSU subscription area; and transmit, to a second V2X device within an RSU management area managed by the RSU device, a second V2X message based on the at least one received first V2X message.

Abstract: The present invention provides a combined heating and hot-water boiler for heating and hot-water. The combined heating and hot-water boiler comprises: a main heat exchanger which heats heating water through heat exchange; a hot-water heat exchanger to which the heating water heated by the main heat exchanger is supplied, and which heats tap water into hot water through heat exchange with the heating water; and a control unit which controls the flow of the heating water having passed through the hot-water heat exchanger to control the formation of at least one of a first flow path for supplying, to an object to be heated, the heating water having passed through the hot-water heat exchanger, and a second flow path for supplying, to the main heat exchanger, the heating water having passed through the hot-water heat exchanger.

Abstract: A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.

Abstract: Methods of detecting one or more genetic variants, including allelic variants, in one or more query samples include providing one or more sensors that each include capture nucleic acids disposed on a functionalized surface of one or more giant magnetoresistance (GMR) sensors. The methods detect the presence of one or more analytes in one or more query samples by measuring magnetoresistance change of the one or more GMR sensors based on determining magnetoresistance before and after passing magnetic particles over the one or more sensors.

Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.

Abstract: The present invention relates to Siphoviridae bacteriophage Vib-ANP-1(accession number KCTC 13075BP) having the ability to specifically kill Vibrio anguillarum bacteria and a genome represented by SEQ ID NO: 1 and isolated from nature, and a method for prevention or treatment of Vibrio anguillarum bacterial infection by using a composition containing the same bacteriophage as an effective ingredient.

Abstract: A battery cell assembly includes a plurality of battery cells, a bus-bar assembly to which electrode leads of the plurality of battery cells are coupled, and a barrier interposed between the plurality of battery cells and coupled to the bus-bar assembly.

Abstract: A coil component includes a support member, an internal coil supported by the support member and including a plurality of coil patterns, and external electrodes connected to the internal coil and including a first layer in contact with the internal coil and a second layer disposed on the first layer. The second layer is a composite layer including a conductive material and a resin. The support member includes first and second surfaces facing the external electrodes, respectively, and one or more of at least a portion of the first surface and at least a portion of the second surface are configured as cut surfaces.

Abstract: A battery cell manufacturing device according to one embodiment of the present disclosure includes a sealing tool that presses a sealing part, in a battery case including a sealing part having a structure in which an electrode assembly is mounted onto a receiving part, and an outer peripheral surface is sealed by heat fusion, wherein the sealing tool comprises a first sealing tool located at an upper part and a second sealing tool located at a lower part with respect to the battery case, and wherein the sealing tool comprises a sealing surface in contact with the sealing part, and at least one pressure sensor is located on the sealing surface.

Abstract: A battery pack includes a cell group including a number of secondary battery cells; a frame accommodating the cell group therein; and a bracket coupled to the frame, linked to the cell group to fix the cell group to the frame, and defining a vent space together with the frame to form a path, through which flames or gas are discharged, when the flames or the gas is generated in one of the secondary battery cells.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a well region extending in a first direction; a gate electrode disposed within the substrate and overlapping the well region; a gate dielectric layer disposed within the substrate and laterally surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure extending in a second direction different from the first direction over the gate dielectric layer; and an insulating layer extending in the second direction between the second protection structure and the gate dielectric layer.

Abstract: A physically unclonable function (PUF) identifier (ID) includes a random fibrous medium and a frame configured to support the random fibrous medium. According to the present disclosure, it is possible to implement a PUF ID that is inexpensive and excellent in encryption performance, and PUF ID reader that reads the PUF ID.

Abstract: A cylindrical battery includes a metal can, an electrode assembly located in the metal can, a cap assembly containing a current interruptive device located on a top of the electrode assembly, an upper insulator located between the cap assembly and the electrode assembly, and at least one spring integrally connected to a lower surface of the current interruptive device.

Abstract: A display device may include a display panel including a display area, a non-display area which may be disposed on a periphery of the display area, and a pad area which may be disposed on one side of the non-display area. The display panel may include data lines disposed in the display area of the display panel along a second direction which intersects a first direction, and connection lines disposed in the display area of the display panel along the first direction. A first data line among the data lines may be connected to a first connection line among the connection lines.

Abstract: The present disclosure provides a particle-based fluid simulation method using multiple processors which is performed in a fluid simulation apparatus, including modeling a simulation region including multiple particles for a fluid, dividing the simulation region into multiple sub-regions, allocating each of the multiple processors to each of the multiple sub-regions, calculating, by each of the multiple processors, flow data of multiple particles for a sub-region corresponding to each of the multiple processors, and performing a fluid simulation based on the result of the calculation. The calculating, by each of the multiple processors, flow data of multiple particles for a sub-region corresponding to each of the multiple processors includes exchanging, by each of the multiple processors, the flow data of the multiple particles with at least one adjacent processor.

Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.

Abstract: Provided is a semiconductor device comprising an active region on a substrate and including first and second sidewalls extending in a first direction and an epitaxial pattern on the active region, wherein the epitaxial pattern includes first and second epitaxial sidewalls extending from the first and second sidewalls, respectively, the first epitaxial sidewall includes a first epitaxial lower sidewall, a first epitaxial upper sidewall, and a first epitaxial connecting sidewall connecting the first epitaxial lower sidewall and the first epitaxial upper sidewall, the second epitaxial sidewall includes a second epitaxial lower sidewall, a second epitaxial upper sidewall, and a second epitaxial connecting sidewall connecting the second epitaxial lower sidewall and the second epitaxial upper sidewall, a distance between the first and second epitaxial upper sidewalls decreases away from the active region, and the first and second epitaxial lower sidewalls extend in parallel to a top surface of the substrate.

Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.

Abstract: A semiconductor device and a method for forming a semiconductor are provided. The semiconductor device includes: a first substrate, a first conductive line disposed on the first substrate, a second substrate opposite to the first substrate, a second conductive line disposed on the second substrate and adjacent to the first conductive line, and a plurality of bonding structures between the first conductive line and the second conductive line. The first conductive line includes a plurality of first segments separated from one another. The second conductive line includes a plurality of second segments separated from one another. Each of the bonding structures is connected to a respective first segment of the plurality of first segments and a respective second segment of the plurality of second segments such that the plurality of first segments, the plurality of bonding structures and the plurality of second segments are connected in series.