Abstract: Provided are a bi-cell for a secondary battery having improved stability which may reduce shrinkage of a separator, and a method of preparing the bi-cell. The bi-cell for a secondary battery having improved stability according to an exemplary embodiment of the present invention is characterized in that a cathode and an anode are alternatingly disposed in a state in which the cathode has one more layer than the anode or the anode has one more layer than the cathode, separators having a bigger size than the cathode and the anode and insulating the cathode and the anode are disposed between the cathode and the anode, and edges of an upper separator and edges of a lower separator, which face to each other having the cathode and the anode disposed therebetween, are attached to each other to form fused portions.

Abstract: The present invention relates to an electric anticorrosive potential measurement electrode unit for measuring an anticorrosive potential of an anticorrosive object (30) buried underground, and comprises: a first electrode unit (10) buried underground near the anticorrosive object (30); and a second electrode unit (20) buried so as to be separated by a distance (D) from the first electrode unit (10) and measuring a comparative potential relative to the first electrode unit (10).

Abstract: The present invention relates to a display device having an integral self-capacitance touch sensor, which can enhance a display property and touch performance by reducing parasitic capacitance and resistance, comprising: a plurality of gate lines and a plurality of data lines that are arranged on a first substrate to cross each other; a plurality of pixel electrodes that are connected to the plurality of gate lines and data lines; a plurality of common and touch electrodes, each of which is formed to overlap some of the plurality of pixel electrodes; and a plurality of routing wires connected to the plurality of common and touch electrodes, respectively, to extend parallel to each other, wherein the plurality of routing wires overlap the data lines with a first insulation film therebetween for covering the data lines, or overlap the gate lines that cross the data lines, and the common and touch electrodes are connected to the routing wires, respectively, through contact holes formed through a second insulatio

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.

Abstract: A display device includes a display panel, an optical film arranged on an upper portion of the display panel and including first and second intaglio pattern portions having different depths from each other, a bonding member configured to contact at least a part of the display panel and a surface of the first intaglio pattern portion and an air layer configured to fill between a surface of the second intaglio pattern portion and the display panel.

Abstract: A semiconductor circuit includes a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit determines a value of a first node based on a voltage level of a clock signal, and a voltage level of an enable signal or a voltage level of a scan enable signal. The second circuit determines a value of a second node based on the voltage levels of the first node and the clock signal. The third circuit determines a value of a third node based on a voltage level of the second node. The fourth circuit determines a value of a fourth node based on the voltage levels of the second node and the clock signal. The third circuit includes a first transistor and a second transistor connected in series with each other and gated to the voltage level of the second node to determine the value of the third node. The fourth circuit includes a third transistor that is gated to the voltage level of the clock signal to electrically connect the third node and the fourth node.

Abstract: An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input signal group and a common input signal group, and a second logic circuit providing a second output signal from a second input signal group and the common input signal group. The first and second logic circuits respectively include first and second transistors formed from a gate electrode, the gate electrode extending in a first direction and receiving a first common input signal of the common input signal group.

Abstract: A method for manufacturing a display panel includes providing a mother substrate that includes a display area and a non-display area, and includes a first substrate, a second substrate facing the first substrate, and a sealant provided between the first substrate and the second substrate, generating a crack on the sealant through irradiation of laser onto the sealant between the first substrate and the second substrate, and cutting a part of the second substrate and a part of the sealant at a position corresponding to the crack.

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.

Abstract: Exemplary embodiments may disclose a flip-flop circuit for inserting a zero-delay bypass mux including a master circuit which is configured to receive a data input, an input clock signal, and a bypass signal, and output an intermediate signal to a first node; and a slave circuit which is configured to receive the intermediate signal at the first node, the input clock signal, and the bypass signal, and output an output clock signal. The bypass signal controls the slave circuit to output one of a buffered input clock signal and a stretched clock signal as the output clock signal based on a logic level of the bypass signal.

Abstract: A multi-bit flip-flop includes: a single scan input pin to receive a scan input signal, a plurality of data input pins to receive first and second data input signals, a first scan flip-flop to select one of the scan input signal and the first data input signal as a first selection signal in response to a scan enable signal and to latch the first selection signal to provide a first output signal, a second scan flip-flop to select one of an internal signal corresponding to the first output signal and the second data input signal as a second selection signal in response to the scan enable signal and to latch the second selection signal to provide a second output signal, and a plurality of output pins to output the first and second output signals, wherein scan paths of the first and second scan flip-flops are connected to each other.

Abstract: A semiconductor device includes a substrate, a first transistor gated by an inverted voltage level of a first input signal to pull up a first node, a second transistor gated by a voltage level of a second input signal to pull down the first node, a third transistor gated by an inverted voltage level of the second input signal to pull up the first node, a fourth transistor gated by a voltage level of the first input signal to pull down the first node, a fifth transistor gated by the voltage level of the second input signal to pull down a second node, a sixth transistor gated by the inverted voltage level of the first input signal to pull up the second node, a seventh transistor gated by the voltage level of the first input signal to pull down the second node, and an eighth transistor gated by the inverted voltage level of the second input signal to pull up the second node.

Abstract: An unbalanced multiplexer and a scan flip-flop including the unbalanced multiplexer, wherein the unbalanced multiplexer includes a first transmission circuit transmitting a first input signal to an output terminal according to a logic state of a selection signal; and a second transmission circuit transmitting a second input signal to the output terminal according to the logic state of the selection signal. A delay characteristic of a first transmission path from a first input terminal to the output terminal along which the first input signal of the first transmission circuit is transmitted, and a delay characteristic of a second transmission path from a second input terminal to the output terminal along which the second input signal of the second transmission circuit is transmitted, are set differently.

Abstract: A semiconductor device includes a first power rail, a second power rail, at least one standard cell and at least one power bridge. The first power rail extends in a first direction over a substrate. The second power rail extends in the first direction over the substrate, and the second power rail is spaced apart from the first power rail in a second direction that intersects the first direction. The at least one standard cell receives a first voltage from the first and the second power rails. The at least one power bridge connects the first power rail and the second power rail in the second direction. The first power rail and the second power rail are formed in a first metal layer and the least one power bridge is formed in a bottom metal layer that is under the first metal layer.

Abstract: A semiconductor device includes: first through fourth active regions spaced apart from one another; a first gate line disposed to overlap with the first and second active regions, but not with the third and fourth active regions, and to extend in a first direction; a second gate line disposed to overlap with the third and fourth active regions, but not with the first and second active regions, and to extend in the first direction while being spaced apart from the first gate line; and a dummy gate line disposed to overlap with the first through fourth active regions and a field region, to be spaced apart from the first and second gate lines in a second direction, and to extend in the first direction, wherein a signal input to the first or second active region is transmitted to the third or fourth active region.

Abstract: A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.

Abstract: An integrated circuit includes a plurality of positive edge-triggered master-slave flip-flop circuits sharing a clock signal. At least one of the positive edge-triggered master-slave flip-flop circuits includes; an input stage that provides a first output signal generated from an input signal in response to the clock signal and an inverted clock signal, a first inverting circuit that generates the inverted clock signal by delaying the clock signal, a transmission gate that receives a second output signal and generates a final output signal, and a second inverting circuit that receives the first output signal and generates the second output signal from the first output signal. The clock signal is applied to an NMOS transistor of the transmission gate and a PMOS transistor of the input stage, and the inverted clock signal is applied to a PMOS transistor of the transmission gate and an NMOS transistor of the input stage.

Abstract: Provided are a reusable polymeric material for removing siloxane compounds in biogas, a method for removing siloxane using the same, and an apparatus therefor, and more particularly, a polyacrylate-based polymer absorbent for removing siloxane compounds in biogas and a method for removing siloxane compounds in biogas. The method for removing siloxane compounds in biogas includes (a) providing the biogas, and b) absorbing the siloxane compounds in a polymer absorbent by passing the biogas through the polymer absorbent according to any one of claims 1 to 5.

Abstract: A semiconductor device may include a master latch that stores an input data signal, using a local power supply voltage and a clock signal, and outputs the input data signal to a first output signal; a slave latch that stores the first output signal, using a global power supply voltage, the clock signal and a retention signal, and outputs a second output signal; a first logic gate that receives input of one signal and another signal of the retention signal, the clock signal and the reset signal, and outputs a first control signal generated by performing a first logical operation; and a second logic gate that receives input of the rest of the retention signal, the clock signal and the reset signal, and the first control signal, and performs a second logical operation to at least one of the master latch and the slave latch.

Abstract: Provided is a semiconductor device including low power retention flip-flop. The semiconductor device includes a first line to which a global power supply voltage is applied, a second line to which a local power supply voltage is applied, the second line being separated from the first line, a first operating circuit connected to the second line to use the local power supply voltage, a first power gating circuit determining whether the local power supply voltage is applied to the first operating circuit and a first retention flip-flop connected to the first line and the second line, wherein the first retention flip-flop comprises a first circuit including a master latch, a second circuit including a slave latch, and a first tri-state inverter connected between the master latch and the slave latch.